Lines Matching +full:0 +full:x300
37 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
43 } while (0)
52 #define EN_LNA0 0x8000
53 #define EN_LNA1 0x4000
54 #define EN_LNA2 0x2000
55 #define EN_LNA3 0x1000
56 #define EN_MIX0 0x0800
57 #define EN_MIX1 0x0400
58 #define EN_MIX2 0x0200
59 #define EN_MIX3 0x0100
60 #define EN_IQADC 0x0040
61 #define EN_PLL 0x0020
62 #define EN_TX 0x0010
63 #define EN_BB 0x0008
64 #define EN_LO 0x0004
65 #define EN_BIAS 0x0001
67 #define EN_IQANA 0x0002
68 #define EN_DIGCLK 0x0080 /* not in the 0x24 reg, only in 0x1b */
69 #define EN_CRYSTAL 0x0002
71 #define EN_UHF 0x22E9
72 #define EN_VHF 0x44E9
73 #define EN_LBD 0x11E9
74 #define EN_SBD 0x44E9
75 #define EN_CAB 0x88E9
78 #define DC_CAL 0x1
79 #define WBD_CAL 0x2
80 #define TEMP_CAL 0x4
81 #define CAPTRIM_CAL 0x8
83 #define KROSUS_PLL_LOCKED 0x800
84 #define KROSUS 0x2
87 #define SOC 0x02
88 #define SOC_7090_P1G_11R1 0x82
89 #define SOC_7090_P1G_21R1 0x8a
90 #define SOC_8090_P1G_11R1 0x86
91 #define SOC_8090_P1G_21R1 0x8e
94 #define P1A_B 0x0
95 #define P1C 0x1
96 #define P1D_E_F 0x3
97 #define P1G 0x7
98 #define P1G_21R2 0xf
100 #define MP001 0x1 /* Single 9090/8096 */
101 #define MP005 0x4 /* Single Sband */
102 #define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
103 #define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_read_reg()
218 return 0; in dib0090_read_reg()
221 state->i2c_write_buffer[0] = reg; in dib0090_read_reg()
223 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib0090_read_reg()
224 state->msg[0].addr = state->config->i2c_address; in dib0090_read_reg()
225 state->msg[0].flags = 0; in dib0090_read_reg()
226 state->msg[0].buf = state->i2c_write_buffer; in dib0090_read_reg()
227 state->msg[0].len = 1; in dib0090_read_reg()
235 ret = 0; in dib0090_read_reg()
237 ret = (state->i2c_read_buffer[0] << 8) in dib0090_read_reg()
248 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_write_reg()
253 state->i2c_write_buffer[0] = reg & 0xff; in dib0090_write_reg()
255 state->i2c_write_buffer[2] = val & 0xff; in dib0090_write_reg()
257 memset(state->msg, 0, sizeof(struct i2c_msg)); in dib0090_write_reg()
258 state->msg[0].addr = state->config->i2c_address; in dib0090_write_reg()
259 state->msg[0].flags = 0; in dib0090_write_reg()
260 state->msg[0].buf = state->i2c_write_buffer; in dib0090_write_reg()
261 state->msg[0].len = 3; in dib0090_write_reg()
267 ret = 0; in dib0090_write_reg()
277 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_read_reg()
279 return 0; in dib0090_fw_read_reg()
282 state->i2c_write_buffer[0] = reg; in dib0090_fw_read_reg()
284 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_read_reg()
291 ret = 0; in dib0090_fw_read_reg()
293 ret = (state->i2c_read_buffer[0] << 8) in dib0090_fw_read_reg()
304 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib0090_fw_write_reg()
309 state->i2c_write_buffer[0] = val >> 8; in dib0090_fw_write_reg()
310 state->i2c_write_buffer[1] = val & 0xff; in dib0090_fw_write_reg()
312 memset(&state->msg, 0, sizeof(struct i2c_msg)); in dib0090_fw_write_reg()
314 state->msg.flags = 0; in dib0090_fw_write_reg()
321 ret = 0; in dib0090_fw_write_reg()
327 … (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); m…
345 v = dib0090_read_reg(state, 0x1a); in dib0090_identify()
347 identity->p1g = 0; in dib0090_identify()
348 identity->in_soc = 0; in dib0090_identify()
350 dprintk("Tuner identification (Version = 0x%04x)\n", v); in dib0090_identify()
355 identity->version = v & 0xff; in dib0090_identify()
356 identity->product = (v >> 8) & 0xf; in dib0090_identify()
361 if ((identity->version & 0x3) == SOC) { in dib0090_identify()
384 switch ((identity->version >> 5) & 0x7) { in dib0090_identify()
401 switch (identity->version & 0x1f) { in dib0090_identify()
425 return 0; in dib0090_identify()
436 u16 v = dib0090_fw_read_reg(state, 0x1a); in dib0090_fw_identify()
437 identity->p1g = 0; in dib0090_fw_identify()
438 identity->in_soc = 0; in dib0090_fw_identify()
440 dprintk("FE: Tuner identification (Version = 0x%04x)\n", v); in dib0090_fw_identify()
445 identity->version = v & 0xff; in dib0090_fw_identify()
446 identity->product = (v >> 8) & 0xf; in dib0090_fw_identify()
451 if ((identity->version & 0x3) == SOC) { in dib0090_fw_identify()
474 switch ((identity->version >> 5) & 0x7) { in dib0090_fw_identify()
491 switch (identity->version & 0x1f) { in dib0090_fw_identify()
515 return 0; in dib0090_fw_identify()
527 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_reset_digital()
531 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remai… in dib0090_reset_digital()
533 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <… in dib0090_reset_digital()
534 if (cfg->clkoutdrive != 0) in dib0090_reset_digital()
535 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
536 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0)); in dib0090_reset_digital()
538 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | … in dib0090_reset_digital()
539 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0)); in dib0090_reset_digital()
542 PllCfg = dib0090_read_reg(state, 0x21); in dib0090_reset_digital()
545 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr… in dib0090_reset_digital()
550 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
554 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
557 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io… in dib0090_reset_digital()
558 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
562 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
567 v = !!(dib0090_read_reg(state, 0x1a) & 0x800); in dib0090_reset_digital()
572 if (i == 0) { in dib0090_reset_digital()
579 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
584 dib0090_write_reg(state, 0x21, PllCfg); in dib0090_reset_digital()
598 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL); in dib0090_fw_reset_digital()
599 …dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL re… in dib0090_fw_reset_digital()
601 dib0090_fw_write_reg(state, 0x20, in dib0090_fw_reset_digital()
602 …((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) … in dib0090_fw_reset_digital()
604 …v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | … in dib0090_fw_reset_digital()
605 if (cfg->clkoutdrive != 0) in dib0090_fw_reset_digital()
611 dib0090_fw_write_reg(state, 0x23, v); in dib0090_fw_reset_digital()
614 PllCfg = dib0090_fw_read_reg(state, 0x21); in dib0090_fw_reset_digital()
617 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr… in dib0090_fw_reset_digital()
621 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
625 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
628 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io… in dib0090_fw_reset_digital()
629 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
633 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
638 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800); in dib0090_fw_reset_digital()
643 if (i == 0) { in dib0090_fw_reset_digital()
650 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
655 dib0090_fw_write_reg(state, 0x21, PllCfg); in dib0090_fw_reset_digital()
665 state->config->sleep(fe, 0); in dib0090_wakeup()
668 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_wakeup()
669 return 0; in dib0090_wakeup()
677 return 0; in dib0090_sleep()
684 dib0090_write_reg(state, 0x04, 0); in dib0090_dcc_freq()
686 dib0090_write_reg(state, 0x04, 1); in dib0090_dcc_freq()
695 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
696 (0 << 9) | 208, /* BB_RAMP4 */
698 (0 << 9) | 440, /* BB_RAMP6 */
706 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
708 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
710 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
711 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
712 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
720 (0 << 10) | 746, /* RF_RAMP6, LNA 1 */
721 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
722 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
724 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
725 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
726 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
733 (0 << 10) | 0, /* RF_RAMP5, LNA 1 = 8dB */ /* 7.47 dB */
734 (0 << 10) | 0, /* RF_RAMP6, LNA 1 */
735 (0 << 10) | 0, /* RF_RAMP7, LNA 2 = 0 dB */
736 (0 << 10) | 0, /* RF_RAMP8, LNA 2 */
738 (0 << 10) | 345, /* GAIN_4_2, LNA 3 */
739 (20 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */ /* 4.96 dB */
740 (0 << 10) | 200, /* RF_RAMP4, LNA 4 */
748 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
750 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
752 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
753 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
754 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
761 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
762 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
764 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
766 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
768 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
775 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
776 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
778 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
780 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
782 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
790 (2 << 9) | 0, /* BB_RAMP3 = 21dB */
791 (0 << 9) | 168, /* BB_RAMP4 */
793 (0 << 9) | 400, /* BB_RAMP6 */
796 #if 0
802 (2 << 9) | 0, /* BB_RAMP3 = 26dB */
803 (0 << 9) | 208, /* BB_RAMP4 */
805 (0 << 9) | 440, /* BB_RAMP6 */
813 (8 << 10) | 743, /* RF_RAMP3, LNA 1 = 0dB */
814 (0 << 10) | 1023, /* RF_RAMP4, LNA 1 */
815 (15 << 10) | 469, /* RF_RAMP5, LNA 2 = 0dB */
816 (0 << 10) | 742, /* RF_RAMP6, LNA 2 */
817 (9 << 10) | 234, /* RF_RAMP7, LNA 3 = 0dB */
818 (0 << 10) | 468, /* RF_RAMP8, LNA 3 */
819 (9 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
820 (0 << 10) | 233, /* GAIN_4_2, LNA 4 */
827 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
828 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
830 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
832 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
834 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
841 (7 << 10) | 0, /* RF_RAMP3, LNA 1 = 13.2dB */
842 (0 << 10) | 290, /* RF_RAMP4, LNA 1 */
844 (0 << 10) | 954, /* RF_RAMP6, LNA 2 */
846 (0 << 10) | 699, /* RF_RAMP8, LNA 3 */
848 (0 << 10) | 580, /* GAIN_4_2, LNA 4 */
851 #if 0
857 (4 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.1dB */
858 (0 << 10) | 508, /* RF_RAMP4, LNA 1 */
860 (0 << 10) | 961, /* RF_RAMP6, LNA 2 */
861 (0 << 10) | 0, /* RF_RAMP7, LNA 3 = 0dB */
862 (0 << 10) | 0, /* RF_RAMP8, LNA 3 */
863 (0 << 10) | 0, /* GAIN_4_1, LNA 4 = 0dB */
864 (0 << 10) | 0, /* GAIN_4_2, LNA 4 */
876 u16 ret = 0; in slopes_to_scale()
877 for (i = 0; i < num; i++) { in slopes_to_scale()
896 wbd &= 0x3ff; in dib0090_wbd_to_db()
898 wbd = 0; in dib0090_wbd_to_db()
925 0x08, 0x0a, 0x0f, 0x01
931 u16 i, v, gain_reg[4] = { 0 }, gain; in dib0090_gain_apply()
944 if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit)) /* overflow */ in dib0090_gain_apply()
945 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_apply()
949 if (state->rf_gain_limit < 0) /*underflow */ in dib0090_gain_apply()
950 state->rf_gain_limit = 0; in dib0090_gain_apply()
953 gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA; in dib0090_gain_apply()
958 /* cannot be less than 0 (only if gain_delta is less than 0 we can have current_gain < 0) */ in dib0090_gain_apply()
959 if (state->current_gain < 0) in dib0090_gain_apply()
960 state->current_gain = 0; in dib0090_gain_apply()
969 if (bb > state->bb_ramp[0]) in dib0090_gain_apply()
970 bb = state->bb_ramp[0]; in dib0090_gain_apply()
973 bb = 0; in dib0090_gain_apply()
976 state->gain[0] = rf; in dib0090_gain_apply()
983 for (i = 0; i < 7; i++) { /* Go over all amplifiers => 5RF amps + 2 BB amps = 7 amps */ in dib0090_gain_apply()
984 …if (g[0] == 0 || ref < (g[1] - g[0])) /* if total gain of the current amp is null or this amp is n… in dib0090_gain_apply()
985 v = 0; /* force the gain to write for the current amp to be null */ in dib0090_gain_apply()
989 v = ((ref - (g[1] - g[0])) * g[2]) / g[0]; in dib0090_gain_apply()
991 if (i == 0) /* LNA 1 reg mapping */ in dib0090_gain_apply()
992 gain_reg[0] = v; in dib0090_gain_apply()
994 gain_reg[0] |= v << 7; in dib0090_gain_apply()
1018 …tk("GA CALC: DB: %3d(rf) + %3d(bb) = %3d gain_reg[0]=%04x gain_reg[1]=%04x gain_reg[2]=%04x gain_r… in dib0090_gain_apply()
1019 gain_reg[0], gain_reg[1], gain_reg[2], gain_reg[3]); in dib0090_gain_apply()
1023 for (i = 0; i < 4; i++) { in dib0090_gain_apply()
1034 state->bb_1_def &= 0xdfff; in dib0090_set_boost()
1047 dib0090_write_reg(state, 0x2a, 0xffff); in dib0090_set_rframp_pwm()
1049 dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a)); in dib0090_set_rframp_pwm()
1051 dib0090_write_regs(state, 0x2c, cfg + 3, 6); in dib0090_set_rframp_pwm()
1052 dib0090_write_regs(state, 0x3e, cfg + 9, 2); in dib0090_set_rframp_pwm()
1058 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp()
1065 dib0090_set_boost(state, cfg[0] > 500); /* we want the boost if the gain is higher that 50dB */ in dib0090_set_bbramp_pwm()
1067 dib0090_write_reg(state, 0x33, 0xffff); in dib0090_set_bbramp_pwm()
1068 dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33)); in dib0090_set_bbramp_pwm()
1069 dib0090_write_regs(state, 0x35, cfg + 3, 4); in dib0090_set_bbramp_pwm()
1122 state->rf_ramp[0], in dib0090_pwm_gain_reset()
1124 state->identity.version & 0x1f); in dib0090_pwm_gain_reset()
1126 if (rf_ramp && ((state->rf_ramp && state->rf_ramp[0] == 0) || in dib0090_pwm_gain_reset()
1128 (state->identity.version & 0x1f) <= P1D_E_F))) { in dib0090_pwm_gain_reset()
1130 en_pwm_rf_mux = 0; in dib0090_pwm_gain_reset()
1134 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11)); in dib0090_pwm_gain_reset()
1136 …/* Set fast servo cutoff to start AGC; 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fas… in dib0090_pwm_gain_reset()
1138 dib0090_write_reg(state, 0x04, 3); in dib0090_pwm_gain_reset()
1140 dib0090_write_reg(state, 0x04, 1); in dib0090_pwm_gain_reset()
1141 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */ in dib0090_pwm_gain_reset()
1150 dib0090_write_reg(state, 0x04, DC_servo_cutoff); in dib0090_set_dc_servo()
1156 u16 adc_val = dib0090_read_reg(state, 0x1d); in dib0090_get_slow_adc_val()
1168 u16 wbd_val = 0; in dib0090_gain_control()
1170 s16 wbd_error = 0, adc_error = 0; in dib0090_gain_control()
1173 state->agc_freeze = 0; in dib0090_gain_control()
1174 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1202 dib0090_write_reg(state, 0x32, 0); in dib0090_gain_control()
1203 dib0090_write_reg(state, 0x39, 0); in dib0090_gain_control()
1207 state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA; in dib0090_gain_control()
1208 state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA; in dib0090_gain_control()
1212 s16 wbd = 0, i, cnt; in dib0090_gain_control()
1222 for (i = 0; i < cnt; i++) { in dib0090_gain_control()
1230 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) { in dib0090_gain_control()
1233 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; in dib0090_gain_control()
1236 state->rf_lt_def &= ltg2 << 10; /* reduce in 3 steps from 7 to 0 */ in dib0090_gain_control()
1240 state->agc_step = 0; in dib0090_gain_control()
1246 adc = (adc * ((s32) 355774) + (((s32) 1) << 20)) >> 21; /* included in [0:-700] */ in dib0090_gain_control()
1259 …ty_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > in dib0090_gain_control()
1260 0) in dib0090_gain_control()
1262 ((state->fe->dtv_property_cache.layer[0].modulation == in dib0090_gain_control()
1265 layer[0].modulation == QAM_16))) in dib0090_gain_control()
1268 0) in dib0090_gain_control()
1276 0) in dib0090_gain_control()
1292 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : nar… in dib0090_gain_control()
1293 dib0090_write_reg(state, 0x04, 0x0); in dib0090_gain_control()
1297 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32)); in dib0090_gain_control()
1298 …dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_gain_control()
1306 apply_gain_immediatly = 0; in dib0090_gain_control()
1329 *rf = state->gain[0]; in dib0090_get_current_gain()
1335 *rflt = (state->rf_lt_def >> 10) & 0x7; in dib0090_get_current_gain()
1353 if (current_temp < 0) in dib0090_get_wbd_target()
1354 current_temp = 0; in dib0090_get_wbd_target()
1359 if (wbd->wbd_gain != 0) in dib0090_get_wbd_target()
1364 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_get_wbd_target()
1390 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8) in dib0090_set_switch()
1393 return 0; in dib0090_set_switch()
1401 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff) in dib0090_set_vga()
1403 return 0; in dib0090_set_vga()
1424 return 0; in dib0090_update_rframp_7090()
1430 25, 0x01,
1431 0x0000,
1432 0x99a0,
1433 0x6008,
1434 0x0000,
1435 0x8bcb,
1436 0x0000,
1437 0x0405,
1438 0x0000,
1439 0x0000,
1440 0x0000,
1441 0xb802,
1442 0x0300,
1443 0x2d12,
1444 0xbac0,
1445 0x7c00,
1446 0xdbb9,
1447 0x0954,
1448 0x0743,
1449 0x8000,
1450 0x0001,
1451 0x0040,
1452 0x0100,
1453 0x0000,
1454 0xe910,
1455 0x149e,
1457 1, 0x1c,
1458 0xff2d,
1460 1, 0x39,
1461 0x0000,
1463 2, 0x1e,
1464 0x07FF,
1465 0x0007,
1467 1, 0x24,
1470 2, 0x3c,
1471 0x3ff,
1472 0x111,
1473 0
1477 1, 0x05,
1478 0xabcd,
1480 1, 0x11,
1481 0x00b4,
1483 1, 0x1c,
1484 0xfffd,
1486 1, 0x40,
1487 0x108,
1488 0
1510 #define POLY_MIN (u8) 0
1519 e2 = dib0090_read_reg(state, 0x26); in dib0090_set_EFUSE()
1520 e4 = dib0090_read_reg(state, 0x28); in dib0090_set_EFUSE()
1523 (state->identity.version == P1G) || (e2 == 0xffff)) { in dib0090_set_EFUSE()
1525 dib0090_write_reg(state, 0x22, 0x10); in dib0090_set_EFUSE()
1526 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff; in dib0090_set_EFUSE()
1537 if (e2 != 0xffff) { in dib0090_set_EFUSE()
1538 c = e2 & 0x3f; in dib0090_set_EFUSE()
1539 n = (e2 >> 12) & 0xf; in dib0090_set_EFUSE()
1540 h = (e2 >> 6) & 0x3f; in dib0090_set_EFUSE()
1551 dib0090_write_reg(state, 0x13, (h << 10)); in dib0090_set_EFUSE()
1553 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */ in dib0090_set_EFUSE()
1562 if (dib0090_identify(fe) < 0) in dib0090_reset()
1566 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */ in dib0090_reset()
1567 return 0; in dib0090_reset()
1571 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2) in dib0090_reset()
1572 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1574 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL)); in dib0090_reset()
1580 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */ in dib0090_reset()
1586 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) in dib0090_reset()
1590 if (state->config->force_crystal_mode != 0) in dib0090_reset()
1591 dib0090_write_reg(state, 0x14, in dib0090_reset()
1594 dib0090_write_reg(state, 0x14, 1); in dib0090_reset()
1596 dib0090_write_reg(state, 0x14, 2); in dib0090_reset()
1597 dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); in dib0090_reset()
1601 return 0; in dib0090_reset()
1613 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_get_offset()
1618 state->adc_diff = dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1621 dib0090_write_reg(state, 0x1f, 0x4); in dib0090_get_offset()
1626 state->adc_diff -= dib0090_read_reg(state, 0x1d); in dib0090_get_offset()
1628 ret = 0; in dib0090_get_offset()
1647 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1648 {0x06, 5, 1, (1 << 13) | (0 << 8) | (26 << 3), 1},
1649 {0x07, 11, 1, (1 << 13) | (0 << 8) | (26 << 3), 0},
1651 {0x06, 0, 0, (1 << 13) | (29 << 8) | (26 << 3), 1},
1652 {0x06, 10, 0, (1 << 13) | (29 << 8) | (26 << 3), 0},
1653 {0},
1657 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1659 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
1660 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
1662 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
1663 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
1664 {0},
1671 if (state->dc->addr == 0x07) in dib0090_set_trim()
1676 *val &= ~(0x1f << state->dc->offset); in dib0090_set_trim()
1684 int ret = 0; in dib0090_dc_offset_calibration()
1692 state->bb6 = 0; in dib0090_dc_offset_calibration()
1693 state->bb7 = 0x040d; in dib0090_dc_offset_calibration()
1696 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ in dib0090_dc_offset_calibration()
1697 dib0090_write_reg(state, 0x24, reg); in dib0090_dc_offset_calibration()
1699 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_dc_offset_calibration()
1700 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); in dib0090_dc_offset_calibration()
1701 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_dc_offset_calibration()
1712 dib0090_write_reg(state, 0x01, state->dc->bb1); in dib0090_dc_offset_calibration()
1713 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); in dib0090_dc_offset_calibration()
1715 state->step = 0; in dib0090_dc_offset_calibration()
1734 if (state->step == 0 && state->adc_diff < 0) { in dib0090_dc_offset_calibration()
1742 if (state->step == 0) { in dib0090_dc_offset_calibration()
1743 if (state->dc->pga && state->adc_diff < 0) in dib0090_dc_offset_calibration()
1744 state->step = 0x10; in dib0090_dc_offset_calibration()
1745 if (state->dc->pga == 0 && state->adc_diff > 0) in dib0090_dc_offset_calibration()
1746 state->step = 0x10; in dib0090_dc_offset_calibration()
1750 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) { in dib0090_dc_offset_calibration()
1751 …/* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuan… in dib0090_dc_offset_calibration()
1766 if (state->dc->addr == 0) /* done */ in dib0090_dc_offset_calibration()
1775 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); in dib0090_dc_offset_calibration()
1776 dib0090_write_reg(state, 0x1f, 0x7); in dib0090_dc_offset_calibration()
1794 if (wbd->wbd_gain != 0) in dib0090_wbd_calibration()
1807 return 0; in dib0090_wbd_calibration()
1810 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); in dib0090_wbd_calibration()
1812 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); in dib0090_wbd_calibration()
1827 return 0; in dib0090_wbd_calibration()
1841 tmp = (0 << 14); in dib0090_set_bandwidth()
1843 state->bb_1_def &= 0x3fff; in dib0090_set_bandwidth()
1846 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ in dib0090_set_bandwidth()
1848 …dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte… in dib0090_set_bandwidth()
1849 …dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa… in dib0090_set_bandwidth()
1851 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n… in dib0090_set_bandwidth()
1853 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */ in dib0090_set_bandwidth()
1854 …dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias… in dib0090_set_bandwidth()
1860 {56000, 0, 9, 48, 6},
1862 {87000, 0, 8, 32, 4},
1864 {115000, 0, 7, 24, 6},
1866 {170000, 0, 6, 16, 4},
1870 {230000, 0, 5, 12, 6},
1872 {340000, 0, 4, 8, 4},
1874 {450000, 0, 3, 6, 6},
1878 {700000, 0, 2, 4, 4},
1882 {1800000, 1, 0, 2, 4},
1885 {2900000, 0, 14, 1, 4},
1892 {184000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1893 {227000, 4, 3, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1894 {380000, 4, 7, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1897 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1898 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1899 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1900 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1901 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1902 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1905 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1906 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1907 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1910 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1911 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1918 {170000, 4, 1, 15, 0x280, 0x2912, 0xb94e, EN_CAB},
1921 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1922 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1923 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1926 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1927 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1928 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1929 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1930 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1931 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1934 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1935 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1936 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1939 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1940 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1946 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
1949 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1950 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1951 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1954 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1955 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1956 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1957 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1958 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1959 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1960 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1963 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1964 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1965 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1968 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1969 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1975 {57000, 0, 11, 48, 6},
1977 {86000, 0, 10, 32, 4},
1979 {115000, 0, 9, 24, 6},
1981 {170000, 0, 8, 16, 4},
1985 {230000, 0, 7, 12, 6},
1987 {340000, 0, 6, 8, 4},
1989 {455000, 0, 5, 6, 6},
1993 {680000, 0, 4, 4, 4},
2000 {2900000, 0, 1, 1, 6},
2006 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2007 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2008 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
2011 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2012 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2013 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2014 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2015 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2016 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
2019 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2020 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2021 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
2024 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
2025 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
2031 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2032 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2033 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2034 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
2040 { 300000, 0 , 3, 0x8105, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2041 { 380000, 0 , 10, 0x810F, 0x2c0, 0x2d12, 0xb84e, EN_CAB },
2042 { 600000, 0 , 10, 0x815E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2043 { 660000, 0 , 5, 0x85E3, 0x280, 0x2d12, 0xb84e, EN_CAB },
2044 { 720000, 0 , 5, 0x852E, 0x280, 0x2d12, 0xb84e, EN_CAB },
2045 { 860000, 0 , 4, 0x85E5, 0x280, 0x2d12, 0xb84e, EN_CAB },
2056 { 300000, 0 , 3, 0x8165, 0x2c0, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2057 { 650000, 0 , 4, 0x815B, 0x280, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2058 { 860000, 0 , 5, 0x84EF, 0x280, 0x2d12, 0xb84e, EN_CAB }, in dib0090_update_tuning_table_7090()
2076 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000) in dib0090_update_tuning_table_7090()
2077 | (tune->lna_bias & 0x7fff)); in dib0090_update_tuning_table_7090()
2078 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f) in dib0090_update_tuning_table_7090()
2079 | ((tune->lna_tune << 6) & 0x07c0)); in dib0090_update_tuning_table_7090()
2080 return 0; in dib0090_update_tuning_table_7090()
2086 int ret = 0; in dib0090_captrim_search()
2087 u16 lo4 = 0xe900; in dib0090_captrim_search()
2092 u8 force_soft_search = 0; in dib0090_captrim_search()
2100 dib0090_write_reg(state, 0x10, 0x2B1); in dib0090_captrim_search()
2101 dib0090_write_reg(state, 0x1e, 0x0032); in dib0090_captrim_search()
2113 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f; in dib0090_captrim_search()
2123 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1); in dib0090_captrim_search()
2124 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2128 dib0090_write_reg(state, 0x18, lo4 | state->captrim); in dib0090_captrim_search()
2137 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0); in dib0090_captrim_search()
2138 dib0090_read_reg(state, 0x40); in dib0090_captrim_search()
2140 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F; in dib0090_captrim_search()
2141 dprintk("***Final Captrim= 0x%x\n", state->fcaptrim); in dib0090_captrim_search()
2149 …if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug… in dib0090_captrim_search()
2178 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim); in dib0090_captrim_search()
2197 state->wbdmux = dib0090_read_reg(state, 0x10); in dib0090_get_temperature()
2198 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); in dib0090_get_temperature()
2200 state->bias = dib0090_read_reg(state, 0x13); in dib0090_get_temperature()
2201 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); in dib0090_get_temperature()
2209 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); in dib0090_get_temperature()
2223 dib0090_write_reg(state, 0x13, state->bias); in dib0090_get_temperature()
2224 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */ in dib0090_get_temperature()
2228 if (state->config->analog_output == 0) in dib0090_get_temperature()
2229 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_get_temperature()
2234 ret = 0; in dib0090_get_temperature()
2240 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
2249 u32 FBDiv, Rest, FREF, VCOF_kHz = 0; in dib0090_tune()
2262 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); in dib0090_tune()
2265 if (state->config->analog_output == 0) in dib0090_tune()
2266 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); in dib0090_tune()
2272 if (state->current_rf == 0) in dib0090_tune()
2281 …access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, oth… in dib0090_tune()
2283 tmp = dib0090_read_reg(state, 0x39); in dib0090_tune()
2284 if ((tmp >> 10) & 0x1) in dib0090_tune()
2285 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); in dib0090_tune()
2296 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) { in dib0090_tune()
2298 u8 found_offset = 0; in dib0090_tune()
2302 while (LUT_offset->RF_freq != 0xffff) { in dib0090_tune()
2314 if (found_offset == 0) in dib0090_tune()
2318 state->tuner_is_tuned = 0; in dib0090_tune()
2319 state->current_rf = 0; in dib0090_tune()
2320 state->current_standard = 0; in dib0090_tune()
2326 tmp = (state->identity.version >> 5) & 0x7; in dib0090_tune()
2348 if (tmp == 0x4 || tmp == 0x7) { in dib0090_tune()
2372 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); in dib0090_tune()
2377 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2384 Rest = 0; in dib0090_tune()
2388 Rest = 0; in dib0090_tune()
2396 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; in dib0090_tune()
2397 * lo6 = 0x0e34 */ in dib0090_tune()
2399 if (Rest == 0) { in dib0090_tune()
2401 lo5 = 0x049f; in dib0090_tune()
2403 lo5 = 0x041f; in dib0090_tune()
2406 lo5 = 0x049e; in dib0090_tune()
2408 lo5 = 0x041d; in dib0090_tune()
2410 lo5 = 0x041c; in dib0090_tune()
2416 lo5 = 0x46f; in dib0090_tune()
2418 lo5 = 0x42f; in dib0090_tune()
2420 lo5 = 0x42c; in dib0090_tune()
2427 lo6 = 0xff98; in dib0090_tune()
2428 else if (state->identity.p1g || (Rest == 0)) in dib0090_tune()
2429 lo6 = 0xfff8; in dib0090_tune()
2431 lo6 = 0xff28; in dib0090_tune()
2437 if (Rest > 0) { in dib0090_tune()
2441 dib0090_write_reg(state, 0x15, (u16) FBDiv); in dib0090_tune()
2442 if (state->config->fref_clock_ratio != 0) in dib0090_tune()
2443 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio); in dib0090_tune()
2445 dib0090_write_reg(state, 0x16, (Den << 8) | 1); in dib0090_tune()
2446 dib0090_write_reg(state, 0x17, (u16) Rest); in dib0090_tune()
2447 dib0090_write_reg(state, 0x19, lo5); in dib0090_tune()
2448 dib0090_write_reg(state, 0x1c, lo6); in dib0090_tune()
2452 lo6 = (lo6 & 0xff9f) | 0x2; in dib0090_tune()
2454 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL); in dib0090_tune()
2471 dib0090_write_reg(state, 0x1e, 0x07ff); in dib0090_tune()
2477 …k("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17… in dib0090_tune()
2478 …m: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x1… in dib0090_tune()
2479 (u32) dib0090_read_reg(state, 0x1c) & 0x3); in dib0090_tune()
2481 #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ in dib0090_tune()
2485 if (wbd->wbd_gain != 0) in dib0090_tune()
2489 dib0090_write_reg(state, 0x10, state->wbdmux); in dib0090_tune()
2493 dib0090_write_reg(state, 0x09, tune->lna_bias); in dib0090_tune()
2494 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim)); in dib0090_tune()
2496 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias); in dib0090_tune()
2498 dib0090_write_reg(state, 0x0c, tune->v2i); in dib0090_tune()
2499 dib0090_write_reg(state, 0x0d, tune->mix); in dib0090_tune()
2500 dib0090_write_reg(state, 0x0e, tune->load); in dib0090_tune()
2505 state->rf_lt_def = 0x7c00; in dib0090_tune()
2538 return 0; in dib0090_set_tune_state()
2548 return 0; in dib0090_get_frequency()
2575 return 0; in dib0090_set_params()
2609 {470, 0, 250, 0, 100, 4},
2611 {1700, 0, 800, 0, 850, 4},
2612 {2900, 0, 250, 0, 100, 6},
2613 {0xFFFF, 0, 0, 0, 0, 0},
2633 if (dib0090_reset(fe) != 0) in dib0090_register()
2660 if (dib0090_fw_reset_digital(fe, st->config) != 0) in dib0090_fw_register()