Lines Matching full:state
237 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) in Read16() argument
239 u8 adr = state->config.demod_address; in Read16()
244 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) in Read16()
251 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) in Read32() argument
253 u8 adr = state->config.demod_address; in Read32()
259 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) in Read32()
267 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) in Write16() argument
269 u8 adr = state->config.demod_address; in Write16()
275 if (i2c_write(state->i2c, adr, mm, 6) < 0) in Write16()
280 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) in Write32() argument
282 u8 adr = state->config.demod_address; in Write32()
289 if (i2c_write(state->i2c, adr, mm, 8) < 0) in Write32()
294 static int write_chunk(struct drxd_state *state, in write_chunk() argument
297 u8 adr = state->config.demod_address; in write_chunk()
305 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { in write_chunk()
312 static int WriteBlock(struct drxd_state *state, in WriteBlock() argument
318 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) in WriteBlock()
327 static int WriteTable(struct drxd_state *state, u8 * pTable) in WriteTable() argument
347 status = WriteBlock(state, Address, Length * 2, pTable, 0); in WriteTable()
357 static int ResetCEFR(struct drxd_state *state) in ResetCEFR() argument
359 return WriteTable(state, state->m_ResetCEFR); in ResetCEFR()
362 static int InitCP(struct drxd_state *state) in InitCP() argument
364 return WriteTable(state, state->m_InitCP); in InitCP()
367 static int InitCE(struct drxd_state *state) in InitCE() argument
370 enum app_env AppEnv = state->app_env_default; in InitCE()
373 status = WriteTable(state, state->m_InitCE); in InitCE()
377 if (state->operation_mode == OM_DVBT_Diversity_Front || in InitCE()
378 state->operation_mode == OM_DVBT_Diversity_End) { in InitCE()
379 AppEnv = state->app_env_diversity; in InitCE()
382 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); in InitCE()
386 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); in InitCE()
389 } else if (AppEnv == APPENV_MOBILE && state->type_A) { in InitCE()
390 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); in InitCE()
393 } else if (AppEnv == APPENV_MOBILE && !state->type_A) { in InitCE()
394 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); in InitCE()
400 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); in InitCE()
407 static int StopOC(struct drxd_state *state) in StopOC() argument
411 u16 ocModeLop = state->m_EcOcRegOcModeLop; in StopOC()
417 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); in StopOC()
421 state->m_EcOcRegSncSncLvl = ocSyncLvl; in StopOC()
425 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); in StopOC()
428 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); in StopOC()
431 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); in StopOC()
434 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); in StopOC()
439 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
442 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StopOC()
448 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); in StopOC()
454 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); in StopOC()
460 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); in StopOC()
463 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); in StopOC()
466 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StopOC()
474 static int StartOC(struct drxd_state *state) in StartOC() argument
480 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); in StartOC()
485 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); in StartOC()
488 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); in StartOC()
493 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); in StartOC()
498 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); in StartOC()
505 static int InitEQ(struct drxd_state *state) in InitEQ() argument
507 return WriteTable(state, state->m_InitEQ); in InitEQ()
510 static int InitEC(struct drxd_state *state) in InitEC() argument
512 return WriteTable(state, state->m_InitEC); in InitEC()
515 static int InitSC(struct drxd_state *state) in InitSC() argument
517 return WriteTable(state, state->m_InitSC); in InitSC()
520 static int InitAtomicRead(struct drxd_state *state) in InitAtomicRead() argument
522 return WriteTable(state, state->m_InitAtomicRead); in InitAtomicRead()
525 static int CorrectSysClockDeviation(struct drxd_state *state);
527 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) in DRX_GetLockStatus() argument
541 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); in DRX_GetLockStatus()
547 if (state->drxd_state != DRXD_STARTED) in DRX_GetLockStatus()
552 CorrectSysClockDeviation(state); in DRX_GetLockStatus()
565 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgIfAgc() argument
577 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
582 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
588 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); in SetCfgIfAgc()
606 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); in SetCfgIfAgc()
612 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); in SetCfgIfAgc()
620 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); in SetCfgIfAgc()
631 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); in SetCfgIfAgc()
634 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); in SetCfgIfAgc()
684 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); in SetCfgIfAgc()
687 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); in SetCfgIfAgc()
690 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); in SetCfgIfAgc()
693 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); in SetCfgIfAgc()
696 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); in SetCfgIfAgc()
710 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) in SetCfgRfAgc() argument
725 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); in SetCfgRfAgc()
732 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); in SetCfgRfAgc()
733 state->m_FeAgRegAgPwd |= in SetCfgRfAgc()
735 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in SetCfgRfAgc()
739 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
746 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
753 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
760 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
773 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
775 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
777 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
781 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
788 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
794 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); in SetCfgRfAgc()
805 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
812 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
824 (state->m_FeAgRegAgPwd) &= in SetCfgRfAgc()
826 (state->m_FeAgRegAgPwd) |= in SetCfgRfAgc()
828 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); in SetCfgRfAgc()
832 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgRfAgc()
839 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgRfAgc()
846 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
853 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); in SetCfgRfAgc()
862 static int ReadIFAgc(struct drxd_state *state, u32 * pValue) in ReadIFAgc() argument
867 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { in ReadIFAgc()
869 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); in ReadIFAgc()
882 u32 R1 = state->if_agc_cfg.R1; in ReadIFAgc()
883 u32 R2 = state->if_agc_cfg.R2; in ReadIFAgc()
884 u32 R3 = state->if_agc_cfg.R3; in ReadIFAgc()
902 static int load_firmware(struct drxd_state *state, const char *fw_name) in load_firmware() argument
906 if (request_firmware(&fw, fw_name, state->dev) < 0) { in load_firmware()
911 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL); in load_firmware()
912 if (!state->microcode) { in load_firmware()
917 state->microcode_length = fw->size; in load_firmware()
922 static int DownloadMicrocode(struct drxd_state *state, in DownloadMicrocode() argument
961 status = WriteBlock(state, Address, BlockSize, in DownloadMicrocode()
972 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) in HI_Command() argument
977 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); in HI_Command()
987 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0); in HI_Command()
991 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); in HI_Command()
995 static int HI_CfgCommand(struct drxd_state *state) in HI_CfgCommand() argument
999 mutex_lock(&state->mutex); in HI_CfgCommand()
1000 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1001 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); in HI_CfgCommand()
1002 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); in HI_CfgCommand()
1003 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); in HI_CfgCommand()
1004 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); in HI_CfgCommand()
1006 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); in HI_CfgCommand()
1008 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == in HI_CfgCommand()
1010 status = Write16(state, HI_RA_RAM_SRV_CMD__A, in HI_CfgCommand()
1013 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL); in HI_CfgCommand()
1014 mutex_unlock(&state->mutex); in HI_CfgCommand()
1018 static int InitHI(struct drxd_state *state) in InitHI() argument
1020 state->hi_cfg_wakeup_key = (state->chip_adr); in InitHI()
1022 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; in InitHI()
1023 return HI_CfgCommand(state); in InitHI()
1026 static int HI_ResetCommand(struct drxd_state *state) in HI_ResetCommand() argument
1030 mutex_lock(&state->mutex); in HI_ResetCommand()
1031 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, in HI_ResetCommand()
1034 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL); in HI_ResetCommand()
1035 mutex_unlock(&state->mutex); in HI_ResetCommand()
1040 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) in DRX_ConfigureI2CBridge() argument
1042 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); in DRX_ConfigureI2CBridge()
1044 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; in DRX_ConfigureI2CBridge()
1046 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; in DRX_ConfigureI2CBridge()
1048 return HI_CfgCommand(state); in DRX_ConfigureI2CBridge()
1057 static int AtomicReadBlock(struct drxd_state *state,
1067 mutex_lock(&state->mutex);
1072 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1075 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1078 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1081 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1084 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1088 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1098 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1106 mutex_unlock(&state->mutex);
1110 static int AtomicReadReg32(struct drxd_state *state,
1118 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1126 static int StopAllProcessors(struct drxd_state *state) in StopAllProcessors() argument
1128 return Write16(state, HI_COMM_EXEC__A, in StopAllProcessors()
1132 static int EnableAndResetMB(struct drxd_state *state) in EnableAndResetMB() argument
1134 if (state->type_A) { in EnableAndResetMB()
1136 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); in EnableAndResetMB()
1140 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); in EnableAndResetMB()
1141 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); in EnableAndResetMB()
1145 static int InitCC(struct drxd_state *state) in InitCC() argument
1147 if (state->osc_clock_freq == 0 || in InitCC()
1148 state->osc_clock_freq > 20000 || in InitCC()
1149 (state->osc_clock_freq % 4000) != 0) { in InitCC()
1150 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); in InitCC()
1154 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); in InitCC()
1155 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | in InitCC()
1157 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); in InitCC()
1158 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); in InitCC()
1159 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); in InitCC()
1164 static int ResetECOD(struct drxd_state *state) in ResetECOD() argument
1168 if (state->type_A) in ResetECOD()
1169 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1171 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); in ResetECOD()
1174 status = WriteTable(state, state->m_ResetECRAM); in ResetECOD()
1176 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); in ResetECOD()
1182 static int SetCfgPga(struct drxd_state *state, int pgaSwitch) in SetCfgPga() argument
1191 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1196 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1201 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1206 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1212 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x000… in SetCfgPga()
1219 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); in SetCfgPga()
1224 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); in SetCfgPga()
1229 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); in SetCfgPga()
1234 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); in SetCfgPga()
1240 …status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x000… in SetCfgPga()
1248 static int InitFE(struct drxd_state *state) in InitFE() argument
1253 status = WriteTable(state, state->m_InitFE_1); in InitFE()
1257 if (state->type_A) { in InitFE()
1258 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1262 if (state->PGA) in InitFE()
1263 status = SetCfgPga(state, 0); in InitFE()
1266 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, in InitFE()
1273 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); in InitFE()
1276 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); in InitFE()
1280 status = WriteTable(state, state->m_InitFE_2); in InitFE()
1289 static int InitFT(struct drxd_state *state) in InitFT() argument
1295 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); in InitFT()
1298 static int SC_WaitForReady(struct drxd_state *state) in SC_WaitForReady() argument
1303 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0); in SC_WaitForReady()
1310 static int SC_SendCommand(struct drxd_state *state, u16 cmd) in SC_SendCommand() argument
1315 Write16(state, SC_RA_RAM_CMD__A, cmd, 0); in SC_SendCommand()
1316 SC_WaitForReady(state); in SC_SendCommand()
1318 ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); in SC_SendCommand()
1328 static int SC_ProcStartCommand(struct drxd_state *state, in SC_ProcStartCommand() argument
1334 mutex_lock(&state->mutex); in SC_ProcStartCommand()
1336 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0); in SC_ProcStartCommand()
1341 SC_WaitForReady(state); in SC_ProcStartCommand()
1342 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_ProcStartCommand()
1343 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_ProcStartCommand()
1344 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_ProcStartCommand()
1346 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); in SC_ProcStartCommand()
1348 mutex_unlock(&state->mutex); in SC_ProcStartCommand()
1352 static int SC_SetPrefParamCommand(struct drxd_state *state, in SC_SetPrefParamCommand() argument
1357 mutex_lock(&state->mutex); in SC_SetPrefParamCommand()
1359 status = SC_WaitForReady(state); in SC_SetPrefParamCommand()
1362 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); in SC_SetPrefParamCommand()
1365 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); in SC_SetPrefParamCommand()
1368 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); in SC_SetPrefParamCommand()
1372 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); in SC_SetPrefParamCommand()
1376 mutex_unlock(&state->mutex); in SC_SetPrefParamCommand()
1381 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1385 mutex_lock(&state->mutex);
1387 status = SC_WaitForReady(state);
1390 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1393 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1397 mutex_unlock(&state->mutex);
1402 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) in ConfigureMPEGOutput() argument
1412 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ in ConfigureMPEGOutput()
1414 if (state->operation_mode == OM_DVBT_Diversity_Front) { in ConfigureMPEGOutput()
1423 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; in ConfigureMPEGOutput()
1431 if (state->insert_rs_byte) { in ConfigureMPEGOutput()
1448 if (state->enable_parallel) in ConfigureMPEGOutput()
1476 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); in ConfigureMPEGOutput()
1479 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); in ConfigureMPEGOutput()
1482 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); in ConfigureMPEGOutput()
1485 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); in ConfigureMPEGOutput()
1492 static int SetDeviceTypeId(struct drxd_state *state) in SetDeviceTypeId() argument
1498 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1502 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); in SetDeviceTypeId()
1507 state->type_A = 0; in SetDeviceTypeId()
1508 state->PGA = 0; in SetDeviceTypeId()
1509 state->diversity = 0; in SetDeviceTypeId()
1511 state->type_A = 1; in SetDeviceTypeId()
1518 state->diversity = 1; in SetDeviceTypeId()
1522 state->PGA = 1; in SetDeviceTypeId()
1525 state->diversity = 1; in SetDeviceTypeId()
1541 state->m_InitAtomicRead = DRXD_InitAtomicRead; in SetDeviceTypeId()
1542 state->m_InitSC = DRXD_InitSC; in SetDeviceTypeId()
1543 state->m_ResetECRAM = DRXD_ResetECRAM; in SetDeviceTypeId()
1544 if (state->type_A) { in SetDeviceTypeId()
1545 state->m_ResetCEFR = DRXD_ResetCEFR; in SetDeviceTypeId()
1546 state->m_InitFE_1 = DRXD_InitFEA2_1; in SetDeviceTypeId()
1547 state->m_InitFE_2 = DRXD_InitFEA2_2; in SetDeviceTypeId()
1548 state->m_InitCP = DRXD_InitCPA2; in SetDeviceTypeId()
1549 state->m_InitCE = DRXD_InitCEA2; in SetDeviceTypeId()
1550 state->m_InitEQ = DRXD_InitEQA2; in SetDeviceTypeId()
1551 state->m_InitEC = DRXD_InitECA2; in SetDeviceTypeId()
1552 if (load_firmware(state, DRX_FW_FILENAME_A2)) in SetDeviceTypeId()
1555 state->m_ResetCEFR = NULL; in SetDeviceTypeId()
1556 state->m_InitFE_1 = DRXD_InitFEB1_1; in SetDeviceTypeId()
1557 state->m_InitFE_2 = DRXD_InitFEB1_2; in SetDeviceTypeId()
1558 state->m_InitCP = DRXD_InitCPB1; in SetDeviceTypeId()
1559 state->m_InitCE = DRXD_InitCEB1; in SetDeviceTypeId()
1560 state->m_InitEQ = DRXD_InitEQB1; in SetDeviceTypeId()
1561 state->m_InitEC = DRXD_InitECB1; in SetDeviceTypeId()
1562 if (load_firmware(state, DRX_FW_FILENAME_B1)) in SetDeviceTypeId()
1565 if (state->diversity) { in SetDeviceTypeId()
1566 state->m_InitDiversityFront = DRXD_InitDiversityFront; in SetDeviceTypeId()
1567 state->m_InitDiversityEnd = DRXD_InitDiversityEnd; in SetDeviceTypeId()
1568 state->m_DisableDiversity = DRXD_DisableDiversity; in SetDeviceTypeId()
1569 state->m_StartDiversityFront = DRXD_StartDiversityFront; in SetDeviceTypeId()
1570 state->m_StartDiversityEnd = DRXD_StartDiversityEnd; in SetDeviceTypeId()
1571 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; in SetDeviceTypeId()
1572 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; in SetDeviceTypeId()
1574 state->m_InitDiversityFront = NULL; in SetDeviceTypeId()
1575 state->m_InitDiversityEnd = NULL; in SetDeviceTypeId()
1576 state->m_DisableDiversity = NULL; in SetDeviceTypeId()
1577 state->m_StartDiversityFront = NULL; in SetDeviceTypeId()
1578 state->m_StartDiversityEnd = NULL; in SetDeviceTypeId()
1579 state->m_DiversityDelay8MHZ = NULL; in SetDeviceTypeId()
1580 state->m_DiversityDelay6MHZ = NULL; in SetDeviceTypeId()
1586 static int CorrectSysClockDeviation(struct drxd_state *state) in CorrectSysClockDeviation() argument
1602 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); in CorrectSysClockDeviation()
1605 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); in CorrectSysClockDeviation()
1609 if (state->type_A) { in CorrectSysClockDeviation()
1617 switch (state->props.bandwidth_hz) { in CorrectSysClockDeviation()
1644 (state->expected_sys_clock_freq)) * in CorrectSysClockDeviation()
1647 (state->expected_sys_clock_freq)); in CorrectSysClockDeviation()
1649 Diff = oscClockDeviation - state->osc_clock_deviation; in CorrectSysClockDeviation()
1652 state->sys_clock_freq = (u16) sysClockFreq; in CorrectSysClockDeviation()
1653 if (oscClockDeviation != state->osc_clock_deviation) { in CorrectSysClockDeviation()
1654 if (state->config.osc_deviation) { in CorrectSysClockDeviation()
1655 state->config.osc_deviation(state->priv, in CorrectSysClockDeviation()
1658 state->osc_clock_deviation = in CorrectSysClockDeviation()
1663 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); in CorrectSysClockDeviation()
1668 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); in CorrectSysClockDeviation()
1671 state->cscd_state = CSCD_SAVED; in CorrectSysClockDeviation()
1678 static int DRX_Stop(struct drxd_state *state) in DRX_Stop() argument
1682 if (state->drxd_state != DRXD_STARTED) in DRX_Stop()
1686 if (state->cscd_state != CSCD_SAVED) { in DRX_Stop()
1688 status = DRX_GetLockStatus(state, &lock); in DRX_Stop()
1693 status = StopOC(state); in DRX_Stop()
1697 state->drxd_state = DRXD_STOPPED; in DRX_Stop()
1699 status = ConfigureMPEGOutput(state, 0); in DRX_Stop()
1703 if (state->type_A) { in DRX_Stop()
1705 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); in DRX_Stop()
1709 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1712 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1717 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1720 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1723 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1726 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1729 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1732 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRX_Stop()
1735 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); in DRX_Stop()
1745 static int SetOperationMode(struct drxd_state *state, int oMode)
1750 if (state->drxd_state != DRXD_STOPPED) {
1755 if (oMode == state->operation_mode) {
1760 if (oMode != OM_Default && !state->diversity) {
1767 status = WriteTable(state, state->m_InitDiversityFront);
1770 status = WriteTable(state, state->m_InitDiversityEnd);
1776 status = WriteTable(state, state->m_DisableDiversity);
1782 state->operation_mode = oMode;
1787 static int StartDiversity(struct drxd_state *state) in StartDiversity() argument
1793 if (state->operation_mode == OM_DVBT_Diversity_Front) { in StartDiversity()
1794 status = WriteTable(state, state->m_StartDiversityFront); in StartDiversity()
1797 } else if (state->operation_mode == OM_DVBT_Diversity_End) { in StartDiversity()
1798 status = WriteTable(state, state->m_StartDiversityEnd); in StartDiversity()
1801 if (state->props.bandwidth_hz == 8000000) { in StartDiversity()
1802 status = WriteTable(state, state->m_DiversityDelay8MHZ); in StartDiversity()
1806 status = WriteTable(state, state->m_DiversityDelay6MHZ); in StartDiversity()
1811 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); in StartDiversity()
1820 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); in StartDiversity()
1828 static int SetFrequencyShift(struct drxd_state *state, in SetFrequencyShift() argument
1831 int negativeShift = (state->tuner_mirrors == channelMirrored); in SetFrequencyShift()
1844 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + in SetFrequencyShift()
1846 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1848 state->fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1850 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); in SetFrequencyShift()
1854 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, in SetFrequencyShift()
1855 1 << 28, state->sys_clock_freq); in SetFrequencyShift()
1857 state->org_fe_fs_add_incr &= 0x0FFFFFFFL; in SetFrequencyShift()
1859 state->org_fe_fs_add_incr = ((1L << 28) - in SetFrequencyShift()
1860 state->org_fe_fs_add_incr); in SetFrequencyShift()
1862 return Write32(state, FE_FS_REG_ADD_INC_LOP__A, in SetFrequencyShift()
1863 state->fe_fs_add_incr, 0); in SetFrequencyShift()
1866 static int SetCfgNoiseCalibration(struct drxd_state *state, in SetCfgNoiseCalibration() argument
1873 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); in SetCfgNoiseCalibration()
1880 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); in SetCfgNoiseCalibration()
1884 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); in SetCfgNoiseCalibration()
1888 if (!state->type_A) { in SetCfgNoiseCalibration()
1889 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); in SetCfgNoiseCalibration()
1892 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); in SetCfgNoiseCalibration()
1901 static int DRX_Start(struct drxd_state *state, s32 off) in DRX_Start() argument
1903 struct dtv_frontend_properties *p = &state->props; in DRX_Start()
1932 if (state->drxd_state != DRXD_STOPPED) in DRX_Start()
1934 status = ResetECOD(state); in DRX_Start()
1937 if (state->type_A) { in DRX_Start()
1938 status = InitSC(state); in DRX_Start()
1942 status = InitFT(state); in DRX_Start()
1945 status = InitCP(state); in DRX_Start()
1948 status = InitCE(state); in DRX_Start()
1951 status = InitEQ(state); in DRX_Start()
1954 status = InitSC(state); in DRX_Start()
1961 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRX_Start()
1964 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRX_Start()
1968 mirrorFreqSpect = (state->props.inversion == INVERSION_ON); in DRX_Start()
1976 if (state->type_A) { in DRX_Start()
1977 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); in DRX_Start()
1987 if (state->type_A) { in DRX_Start()
1988 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); in DRX_Start()
2021 if (state->type_A) { in DRX_Start()
2022 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2025 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); in DRX_Start()
2051 if (state->type_A) { in DRX_Start()
2052 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2055 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); in DRX_Start()
2080 if (state->type_A) { in DRX_Start()
2081 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2084 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); in DRX_Start()
2112 if (state->type_A) { in DRX_Start()
2113 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2116 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); in DRX_Start()
2149 if (state->type_A) { in DRX_Start()
2150 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); in DRX_Start()
2153 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); in DRX_Start()
2156 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); in DRX_Start()
2159 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); in DRX_Start()
2162 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); in DRX_Start()
2166 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); in DRX_Start()
2169 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); in DRX_Start()
2172 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); in DRX_Start()
2175 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); in DRX_Start()
2182 if (state->type_A) { in DRX_Start()
2183 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); in DRX_Start()
2186 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); in DRX_Start()
2189 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2192 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); in DRX_Start()
2195 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2199 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); in DRX_Start()
2202 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); in DRX_Start()
2205 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); in DRX_Start()
2208 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); in DRX_Start()
2216 if (state->type_A) { in DRX_Start()
2217 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); in DRX_Start()
2220 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); in DRX_Start()
2223 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); in DRX_Start()
2226 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); in DRX_Start()
2229 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); in DRX_Start()
2233 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); in DRX_Start()
2236 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); in DRX_Start()
2239 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); in DRX_Start()
2242 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); in DRX_Start()
2257 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); in DRX_Start()
2263 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); in DRX_Start()
2273 if (state->type_A) { in DRX_Start()
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); in DRX_Start()
2284 if (state->type_A) { in DRX_Start()
2285 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); in DRX_Start()
2292 if (state->type_A) { in DRX_Start()
2293 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); in DRX_Start()
2300 if (state->type_A) { in DRX_Start()
2301 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); in DRX_Start()
2308 if (state->type_A) { in DRX_Start()
2309 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); in DRX_Start()
2334 status = Write16(state, in DRX_Start()
2341 status = Write16(state, in DRX_Start()
2348 status = Write16(state, in DRX_Start()
2357 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); in DRX_Start()
2363 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); in DRX_Start()
2377 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); in DRX_Start()
2382 status = SetCfgNoiseCalibration(state, &state->noise_cal); in DRX_Start()
2386 if (state->cscd_state == CSCD_INIT) { in DRX_Start()
2388 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); in DRX_Start()
2392 state->cscd_state = CSCD_SET; in DRX_Start()
2398 feIfIncr = MulDiv32(state->sys_clock_freq * 1000, in DRX_Start()
2400 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); in DRX_Start()
2403 …status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_IN… in DRX_Start()
2409 SetFrequencyShift(state, off, mirrorFreqSpect); in DRX_Start()
2414 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); in DRX_Start()
2417 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); in DRX_Start()
2429 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); in DRX_Start()
2434 …status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_… in DRX_Start()
2438 status = StartOC(state); in DRX_Start()
2442 if (state->operation_mode != OM_Default) { in DRX_Start()
2443 status = StartDiversity(state); in DRX_Start()
2448 state->drxd_state = DRXD_STARTED; in DRX_Start()
2454 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) in CDRXD() argument
2474 u32 ulClock = state->config.clock; in CDRXD()
2484 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2485 state->if_agc_cfg.outputLevel = 0; in CDRXD()
2486 state->if_agc_cfg.settleLevel = 140; in CDRXD()
2487 state->if_agc_cfg.minOutputLevel = 0; in CDRXD()
2488 state->if_agc_cfg.maxOutputLevel = 1023; in CDRXD()
2489 state->if_agc_cfg.speed = 904; in CDRXD()
2492 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2493 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); in CDRXD()
2501 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2502 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); in CDRXD()
2503 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); in CDRXD()
2504 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); in CDRXD()
2505 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); in CDRXD()
2508 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); in CDRXD()
2509 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); in CDRXD()
2510 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); in CDRXD()
2512 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); in CDRXD()
2513 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); in CDRXD()
2514 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); in CDRXD()
2516 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2519 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; in CDRXD()
2520 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); in CDRXD()
2528 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; in CDRXD()
2529 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); in CDRXD()
2530 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); in CDRXD()
2531 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); in CDRXD()
2532 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); in CDRXD()
2536 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; in CDRXD()
2539 state->app_env_default = (enum app_env) in CDRXD()
2542 state->app_env_diversity = (enum app_env) in CDRXD()
2547 state->noise_cal.cpOpt = 0; in CDRXD()
2548 state->noise_cal.cpNexpOfs = 40; in CDRXD()
2549 state->noise_cal.tdCal2k = -40; in CDRXD()
2550 state->noise_cal.tdCal8k = -24; in CDRXD()
2553 state->noise_cal.cpOpt = 1; in CDRXD()
2554 state->noise_cal.cpNexpOfs = 0; in CDRXD()
2555 state->noise_cal.tdCal2k = -21; in CDRXD()
2556 state->noise_cal.tdCal8k = -24; in CDRXD()
2558 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); in CDRXD()
2560 state->chip_adr = (state->config.demod_address << 1) | 1; in CDRXD()
2563 state->m_HiI2cPatch = DRXD_HiI2cPatch_1; in CDRXD()
2566 state->m_HiI2cPatch = DRXD_HiI2cPatch_3; in CDRXD()
2569 state->m_HiI2cPatch = NULL; in CDRXD()
2573 state->intermediate_freq = (u16) (IntermediateFrequency / 1000); in CDRXD()
2575 state->expected_sys_clock_freq = 48000; in CDRXD()
2577 state->sys_clock_freq = 48000; in CDRXD()
2578 state->osc_clock_freq = (u16) ulClock; in CDRXD()
2579 state->osc_clock_deviation = 0; in CDRXD()
2580 state->cscd_state = CSCD_INIT; in CDRXD()
2581 state->drxd_state = DRXD_UNINITIALIZED; in CDRXD()
2583 state->PGA = 0; in CDRXD()
2584 state->type_A = 0; in CDRXD()
2585 state->tuner_mirrors = 0; in CDRXD()
2588 state->insert_rs_byte = state->config.insert_rs_byte; in CDRXD()
2589 state->enable_parallel = (ulSerialMode != 1); in CDRXD()
2594 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * in CDRXD()
2598 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * in CDRXD()
2601 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in CDRXD()
2602 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ in CDRXD()
2603 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in CDRXD()
2607 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) in DRXD_init() argument
2612 if (state->init_done) in DRXD_init()
2615 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in DRXD_init()
2618 state->operation_mode = OM_Default; in DRXD_init()
2620 status = SetDeviceTypeId(state); in DRXD_init()
2625 if (!state->type_A && state->m_HiI2cPatch) { in DRXD_init()
2626 status = WriteTable(state, state->m_HiI2cPatch); in DRXD_init()
2631 if (state->type_A) { in DRXD_init()
2634 status = Write16(state, 0x43012D, 0x047f, 0); in DRXD_init()
2639 status = HI_ResetCommand(state); in DRXD_init()
2643 status = StopAllProcessors(state); in DRXD_init()
2646 status = InitCC(state); in DRXD_init()
2650 state->osc_clock_deviation = 0; in DRXD_init()
2652 if (state->config.osc_deviation) in DRXD_init()
2653 state->osc_clock_deviation = in DRXD_init()
2654 state->config.osc_deviation(state->priv, 0, 0); in DRXD_init()
2658 s32 devA = (s32) (state->osc_clock_deviation) * in DRXD_init()
2659 (s32) (state->expected_sys_clock_freq); in DRXD_init()
2672 state->sys_clock_freq = in DRXD_init()
2673 (u16) ((state->expected_sys_clock_freq) + in DRXD_init()
2676 status = InitHI(state); in DRXD_init()
2679 status = InitAtomicRead(state); in DRXD_init()
2683 status = EnableAndResetMB(state); in DRXD_init()
2686 if (state->type_A) { in DRXD_init()
2687 status = ResetCEFR(state); in DRXD_init()
2692 status = DownloadMicrocode(state, fw, fw_size); in DRXD_init()
2696 status = DownloadMicrocode(state, state->microcode, state->microcode_length); in DRXD_init()
2701 if (state->PGA) { in DRXD_init()
2702 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; in DRXD_init()
2703 SetCfgPga(state, 0); /* PGA = 0 dB */ in DRXD_init()
2705 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; in DRXD_init()
2708 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; in DRXD_init()
2710 status = InitFE(state); in DRXD_init()
2713 status = InitFT(state); in DRXD_init()
2716 status = InitCP(state); in DRXD_init()
2719 status = InitCE(state); in DRXD_init()
2722 status = InitEQ(state); in DRXD_init()
2725 status = InitEC(state); in DRXD_init()
2728 status = InitSC(state); in DRXD_init()
2732 status = SetCfgIfAgc(state, &state->if_agc_cfg); in DRXD_init()
2735 status = SetCfgRfAgc(state, &state->rf_agc_cfg); in DRXD_init()
2739 state->cscd_state = CSCD_INIT; in DRXD_init()
2740 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2743 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); in DRXD_init()
2755 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); in DRXD_init()
2759 status = StopOC(state); in DRXD_init()
2763 state->drxd_state = DRXD_STOPPED; in DRXD_init()
2764 state->init_done = 1; in DRXD_init()
2770 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus) in DRXD_status() argument
2772 DRX_GetLockStatus(state, pLockStatus); in DRXD_status()
2776 ConfigureMPEGOutput(state, 1); in DRXD_status()
2778 /*DRX_GetLockStatus(state, pLockStatus); */ in DRXD_status()
2790 struct drxd_state *state = fe->demodulator_priv; in drxd_read_signal_strength() local
2794 res = ReadIFAgc(state, &value); in drxd_read_signal_strength()
2804 struct drxd_state *state = fe->demodulator_priv; in drxd_read_status() local
2807 DRXD_status(state, &lock); in drxd_read_status()
2827 struct drxd_state *state = fe->demodulator_priv; in drxd_init() local
2829 return DRXD_init(state, NULL, 0); in drxd_init()
2834 struct drxd_state *state = fe->demodulator_priv; in drxd_config_i2c() local
2836 if (state->config.disable_i2c_gate_ctrl == 1) in drxd_config_i2c()
2839 return DRX_ConfigureI2CBridge(state, onoff); in drxd_config_i2c()
2871 struct drxd_state *state = fe->demodulator_priv; in drxd_sleep() local
2873 ConfigureMPEGOutput(state, 0); in drxd_sleep()
2885 struct drxd_state *state = fe->demodulator_priv; in drxd_set_frontend() local
2888 state->props = *p; in drxd_set_frontend()
2889 DRX_Stop(state); in drxd_set_frontend()
2899 return DRX_Start(state, off); in drxd_set_frontend()
2904 struct drxd_state *state = fe->demodulator_priv; in drxd_release() local
2906 kfree(state); in drxd_release()
2944 struct drxd_state *state = NULL; in drxd_attach() local
2946 state = kzalloc(sizeof(*state), GFP_KERNEL); in drxd_attach()
2947 if (!state) in drxd_attach()
2950 state->ops = drxd_ops; in drxd_attach()
2951 state->dev = dev; in drxd_attach()
2952 state->config = *config; in drxd_attach()
2953 state->i2c = i2c; in drxd_attach()
2954 state->priv = priv; in drxd_attach()
2956 mutex_init(&state->mutex); in drxd_attach()
2958 if (Read16(state, 0, NULL, 0) < 0) in drxd_attach()
2961 state->frontend.ops = drxd_ops; in drxd_attach()
2962 state->frontend.demodulator_priv = state; in drxd_attach()
2963 ConfigureMPEGOutput(state, 0); in drxd_attach()
2965 CDRXD(state, state->config.IF ? state->config.IF : 36000000); in drxd_attach()
2966 InitHI(state); in drxd_attach()
2968 return &state->frontend; in drxd_attach()
2972 kfree(state); in drxd_attach()