Lines Matching +full:0 +full:x70
39 } while (0)
49 0x23, 0x05,
50 0x08, 0x03,
51 0x0c, 0x00,
52 0x21, 0x54,
53 0x25, 0x82,
54 0x27, 0x31,
55 0x30, 0x08,
56 0x31, 0x40,
57 0x32, 0x32,
58 0x33, 0x35,
59 0x35, 0xff,
60 0x3a, 0x00,
61 0x37, 0x10,
62 0x38, 0x10,
63 0x39, 0x02,
64 0x42, 0x60,
65 0x4a, 0x40,
66 0x4b, 0x04,
67 0x4d, 0x91,
68 0x5d, 0xc8,
69 0x50, 0x77,
70 0x51, 0x77,
71 0x52, 0x36,
72 0x53, 0x36,
73 0x56, 0x01,
74 0x63, 0x43,
75 0x64, 0x30,
76 0x65, 0x40,
77 0x68, 0x26,
78 0x69, 0x4c,
79 0x70, 0x20,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0x40,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x60,
88 0x71, 0x70,
89 0x72, 0x04,
90 0x73, 0x00,
91 0x70, 0x80,
92 0x71, 0x70,
93 0x72, 0x04,
94 0x73, 0x00,
95 0x70, 0xa0,
96 0x71, 0x70,
97 0x72, 0x04,
98 0x73, 0x00,
99 0x70, 0x1f,
100 0x76, 0x00,
101 0x77, 0xd1,
102 0x78, 0x0c,
103 0x79, 0x80,
104 0x7f, 0x04,
105 0x7c, 0x00,
106 0x80, 0x86,
107 0x81, 0xa6,
108 0x85, 0x04,
109 0xcd, 0xf4,
110 0x90, 0x33,
111 0xa0, 0x44,
112 0xc0, 0x18,
113 0xc3, 0x10,
114 0xc4, 0x08,
115 0xc5, 0x80,
116 0xc6, 0x80,
117 0xc7, 0x0a,
118 0xc8, 0x1a,
119 0xc9, 0x80,
120 0xfe, 0x92,
121 0xe0, 0xf8,
122 0xe6, 0x8b,
123 0xd0, 0x40,
124 0xf8, 0x20,
125 0xfa, 0x0f,
126 0xfd, 0x20,
127 0xad, 0x20,
128 0xae, 0x07,
129 0xb8, 0x00,
134 0x23, 0x0f,
135 0x08, 0x07,
136 0x0c, 0x00,
137 0x21, 0x54,
138 0x25, 0x82,
139 0x27, 0x31,
140 0x30, 0x08,
141 0x31, 0x32,
142 0x32, 0x32,
143 0x33, 0x35,
144 0x35, 0xff,
145 0x3a, 0x00,
146 0x37, 0x10,
147 0x38, 0x10,
148 0x39, 0x02,
149 0x42, 0x60,
150 0x4a, 0x80,
151 0x4b, 0x04,
152 0x4d, 0x81,
153 0x5d, 0x88,
154 0x50, 0x36,
155 0x51, 0x36,
156 0x52, 0x36,
157 0x53, 0x36,
158 0x63, 0x60,
159 0x64, 0x10,
160 0x65, 0x10,
161 0x68, 0x04,
162 0x69, 0x29,
163 0x70, 0x20,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0x40,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x60,
172 0x71, 0x70,
173 0x72, 0x04,
174 0x73, 0x00,
175 0x70, 0x80,
176 0x71, 0x70,
177 0x72, 0x04,
178 0x73, 0x00,
179 0x70, 0xa0,
180 0x71, 0x70,
181 0x72, 0x04,
182 0x73, 0x00,
183 0x70, 0x1f,
184 0xa0, 0x44,
185 0xc0, 0x08,
186 0xc1, 0x10,
187 0xc2, 0x08,
188 0xc3, 0x10,
189 0xc4, 0x08,
190 0xc5, 0xf0,
191 0xc6, 0xf0,
192 0xc7, 0x0a,
193 0xc8, 0x1a,
194 0xc9, 0x80,
195 0xca, 0x23,
196 0xcb, 0x24,
197 0xce, 0x74,
198 0x90, 0x03,
199 0x76, 0x80,
200 0x77, 0x42,
201 0x78, 0x0a,
202 0x79, 0x80,
203 0xad, 0x40,
204 0xae, 0x07,
205 0x7f, 0xd4,
206 0x7c, 0x00,
207 0x80, 0xa8,
208 0x81, 0xda,
209 0x7c, 0x01,
210 0x80, 0xda,
211 0x81, 0xec,
212 0x7c, 0x02,
213 0x80, 0xca,
214 0x81, 0xeb,
215 0x7c, 0x03,
216 0x80, 0xba,
217 0x81, 0xdb,
218 0x85, 0x08,
219 0x86, 0x00,
220 0x87, 0x02,
221 0x89, 0x80,
222 0x8b, 0x44,
223 0x8c, 0xaa,
224 0x8a, 0x10,
225 0xba, 0x00,
226 0xf5, 0x04,
227 0xfe, 0x44,
228 0xd2, 0x32,
229 0xb8, 0x00,
244 .flags = 0, .buf = buf, .len = 2 }; in ds3000_writereg()
247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); in ds3000_writereg()
251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n", in ds3000_writereg()
256 return 0; in ds3000_writereg()
264 ds3000_writereg(state, 0x03, 0x12); in ds3000_i2c_gate_ctrl()
266 ds3000_writereg(state, 0x03, 0x02); in ds3000_i2c_gate_ctrl()
268 return 0; in ds3000_i2c_gate_ctrl()
275 int i, ret = 0; in ds3000_writeFW()
286 msg.flags = 0; in ds3000_writeFW()
290 for (i = 0; i < len; i += 32) { in ds3000_writeFW()
293 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); in ds3000_writeFW()
297 printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n", in ds3000_writeFW()
303 ret = 0; in ds3000_writeFW()
315 u8 b1[] = { 0 }; in ds3000_readreg()
319 .flags = 0, in ds3000_readreg()
333 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); in ds3000_readreg()
337 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); in ds3000_readreg()
339 return b1[0]; in ds3000_readreg()
349 int ret = 0; in ds3000_firmware_ondemand()
353 ret = ds3000_readreg(state, 0xb2); in ds3000_firmware_ondemand()
354 if (ret < 0) in ds3000_firmware_ondemand()
377 ret == 0 ? "complete" : "failed"); in ds3000_firmware_ondemand()
386 int ret = 0; in ds3000_load_firmware()
391 fw->data[0], in ds3000_load_firmware()
397 ds3000_writereg(state, 0xb2, 0x01); in ds3000_load_firmware()
399 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size); in ds3000_load_firmware()
400 ds3000_writereg(state, 0xb2, 0x00); in ds3000_load_firmware()
413 data = ds3000_readreg(state, 0xa2); in ds3000_set_voltage()
414 data |= 0x03; /* bit0 V/H, bit1 off/on */ in ds3000_set_voltage()
418 data &= ~0x03; in ds3000_set_voltage()
421 data &= ~0x03; in ds3000_set_voltage()
422 data |= 0x01; in ds3000_set_voltage()
428 ds3000_writereg(state, 0xa2, data); in ds3000_set_voltage()
430 return 0; in ds3000_set_voltage()
439 *status = 0; in ds3000_read_status()
443 lock = ds3000_readreg(state, 0xd1); in ds3000_read_status()
444 if ((lock & 0x07) == 0x07) in ds3000_read_status()
451 lock = ds3000_readreg(state, 0x0d); in ds3000_read_status()
452 if ((lock & 0x8f) == 0x8f) in ds3000_read_status()
463 state->config->set_lock_led(fe, *status == 0 ? 0 : 1); in ds3000_read_status()
465 dprintk("%s: status = 0x%02x\n", __func__, lock); in ds3000_read_status()
467 return 0; in ds3000_read_status()
484 ds3000_writereg(state, 0xf9, 0x04); in ds3000_read_ber()
486 data = ds3000_readreg(state, 0xf8); in ds3000_read_ber()
488 if ((data & 0x10) == 0) { in ds3000_read_ber()
492 *ber = (ds3000_readreg(state, 0xf7) << 8) | in ds3000_read_ber()
493 ds3000_readreg(state, 0xf6); in ds3000_read_ber()
497 data |= 0x10; in ds3000_read_ber()
498 ds3000_writereg(state, 0xf8, data); in ds3000_read_ber()
499 ds3000_writereg(state, 0xf8, data); in ds3000_read_ber()
503 *ber = 0xffffffff; in ds3000_read_ber()
507 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | in ds3000_read_ber()
508 (ds3000_readreg(state, 0xd6) << 8) | in ds3000_read_ber()
509 ds3000_readreg(state, 0xd5); in ds3000_read_ber()
511 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | in ds3000_read_ber()
512 ds3000_readreg(state, 0xf7); in ds3000_read_ber()
515 ds3000_writereg(state, 0xd1, 0x01); in ds3000_read_ber()
517 ds3000_writereg(state, 0xf9, 0x01); in ds3000_read_ber()
519 ds3000_writereg(state, 0xf9, 0x00); in ds3000_read_ber()
521 ds3000_writereg(state, 0xd1, 0x00); in ds3000_read_ber()
526 *ber = 0xffffffff; in ds3000_read_ber()
532 return 0; in ds3000_read_ber()
541 return 0; in ds3000_read_signal_strength()
552 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, in ds3000_read_snr()
553 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, in ds3000_read_snr()
554 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 in ds3000_read_snr()
557 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, in ds3000_read_snr()
558 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, in ds3000_read_snr()
559 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, in ds3000_read_snr()
560 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, in ds3000_read_snr()
561 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, in ds3000_read_snr()
562 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, in ds3000_read_snr()
563 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, in ds3000_read_snr()
564 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, in ds3000_read_snr()
565 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, in ds3000_read_snr()
566 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, in ds3000_read_snr()
567 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, in ds3000_read_snr()
568 0x49e9, 0x4a20, 0x4a57 in ds3000_read_snr()
575 snr_reading = ds3000_readreg(state, 0xff); in ds3000_read_snr()
577 if (snr_reading == 0) in ds3000_read_snr()
578 *snr = 0x0000; in ds3000_read_snr()
587 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, in ds3000_read_snr()
591 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + in ds3000_read_snr()
592 (ds3000_readreg(state, 0x8d) << 4); in ds3000_read_snr()
593 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); in ds3000_read_snr()
595 if (tmp == 0) { in ds3000_read_snr()
596 *snr = 0x0000; in ds3000_read_snr()
597 return 0; in ds3000_read_snr()
599 if (dvbs2_noise_reading == 0) { in ds3000_read_snr()
600 snr_value = 0x0013; in ds3000_read_snr()
603 *snr = 0xffff; in ds3000_read_snr()
604 return 0; in ds3000_read_snr()
620 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, in ds3000_read_snr()
627 return 0; in ds3000_read_snr()
642 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | in ds3000_read_ucblocks()
643 ds3000_readreg(state, 0xf4); in ds3000_read_ucblocks()
644 data = ds3000_readreg(state, 0xf8); in ds3000_read_ucblocks()
646 data &= ~0x20; in ds3000_read_ucblocks()
647 ds3000_writereg(state, 0xf8, data); in ds3000_read_ucblocks()
649 data |= 0x20; in ds3000_read_ucblocks()
650 ds3000_writereg(state, 0xf8, data); in ds3000_read_ucblocks()
653 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | in ds3000_read_ucblocks()
654 ds3000_readreg(state, 0xe1); in ds3000_read_ucblocks()
665 return 0; in ds3000_read_ucblocks()
679 data = ds3000_readreg(state, 0xa2); in ds3000_set_tone()
680 data &= ~0xc0; in ds3000_set_tone()
681 ds3000_writereg(state, 0xa2, data); in ds3000_set_tone()
686 data = ds3000_readreg(state, 0xa1); in ds3000_set_tone()
687 data &= ~0x43; in ds3000_set_tone()
688 data |= 0x04; in ds3000_set_tone()
689 ds3000_writereg(state, 0xa1, data); in ds3000_set_tone()
693 data = ds3000_readreg(state, 0xa2); in ds3000_set_tone()
694 data |= 0x80; in ds3000_set_tone()
695 ds3000_writereg(state, 0xa2, data); in ds3000_set_tone()
699 return 0; in ds3000_set_tone()
711 for (i = 0 ; i < d->msg_len;) { in ds3000_send_diseqc_msg()
712 dprintk("0x%02x", d->msg[i]); in ds3000_send_diseqc_msg()
718 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
719 data &= ~0xc0; in ds3000_send_diseqc_msg()
720 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
723 for (i = 0; i < d->msg_len; i++) in ds3000_send_diseqc_msg()
724 ds3000_writereg(state, 0xa3 + i, d->msg[i]); in ds3000_send_diseqc_msg()
726 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
729 data &= ~0xf8; in ds3000_send_diseqc_msg()
732 data |= ((d->msg_len - 1) << 3) | 0x07; in ds3000_send_diseqc_msg()
733 ds3000_writereg(state, 0xa1, data); in ds3000_send_diseqc_msg()
736 for (i = 0; i < 15; i++) { in ds3000_send_diseqc_msg()
737 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
738 if ((data & 0x40) == 0) in ds3000_send_diseqc_msg()
745 data = ds3000_readreg(state, 0xa1); in ds3000_send_diseqc_msg()
746 data &= ~0x80; in ds3000_send_diseqc_msg()
747 data |= 0x40; in ds3000_send_diseqc_msg()
748 ds3000_writereg(state, 0xa1, data); in ds3000_send_diseqc_msg()
750 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
751 data &= ~0xc0; in ds3000_send_diseqc_msg()
752 data |= 0x80; in ds3000_send_diseqc_msg()
753 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
758 data = ds3000_readreg(state, 0xa2); in ds3000_send_diseqc_msg()
759 data &= ~0xc0; in ds3000_send_diseqc_msg()
760 data |= 0x80; in ds3000_send_diseqc_msg()
761 ds3000_writereg(state, 0xa2, data); in ds3000_send_diseqc_msg()
763 return 0; in ds3000_send_diseqc_msg()
776 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
777 data &= ~0xc0; in ds3000_diseqc_send_burst()
778 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
783 ds3000_writereg(state, 0xa1, 0x02); in ds3000_diseqc_send_burst()
786 ds3000_writereg(state, 0xa1, 0x01); in ds3000_diseqc_send_burst()
791 for (i = 0; i < 5; i++) { in ds3000_diseqc_send_burst()
792 data = ds3000_readreg(state, 0xa1); in ds3000_diseqc_send_burst()
793 if ((data & 0x40) == 0) in ds3000_diseqc_send_burst()
799 data = ds3000_readreg(state, 0xa1); in ds3000_diseqc_send_burst()
800 data &= ~0x80; in ds3000_diseqc_send_burst()
801 data |= 0x40; in ds3000_diseqc_send_burst()
802 ds3000_writereg(state, 0xa1, data); in ds3000_diseqc_send_burst()
804 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
805 data &= ~0xc0; in ds3000_diseqc_send_burst()
806 data |= 0x80; in ds3000_diseqc_send_burst()
807 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
812 data = ds3000_readreg(state, 0xa2); in ds3000_diseqc_send_burst()
813 data &= ~0xc0; in ds3000_diseqc_send_burst()
814 data |= 0x80; in ds3000_diseqc_send_burst()
815 ds3000_writereg(state, 0xa2, data); in ds3000_diseqc_send_burst()
817 return 0; in ds3000_diseqc_send_burst()
825 state->config->set_lock_led(fe, 0); in ds3000_release()
848 state->prevUCBS2 = 0; in ds3000_attach()
851 ret = ds3000_readreg(state, 0x00) & 0xfe; in ds3000_attach()
852 if (ret != 0xe0) { in ds3000_attach()
859 ds3000_readreg(state, 0x02), in ds3000_attach()
860 ds3000_readreg(state, 0x01)); in ds3000_attach()
886 if (tmp < 0) in ds3000_set_carrier_offset()
889 ds3000_writereg(state, 0x5f, tmp >> 8); in ds3000_set_carrier_offset()
890 ds3000_writereg(state, 0x5e, tmp & 0xff); in ds3000_set_carrier_offset()
892 return 0; in ds3000_set_carrier_offset()
909 state->config->set_ts_params(fe, 0); in ds3000_set_frontend()
915 ds3000_writereg(state, 0x07, 0x80); in ds3000_set_frontend()
916 ds3000_writereg(state, 0x07, 0x00); in ds3000_set_frontend()
918 ds3000_writereg(state, 0xb2, 0x01); in ds3000_set_frontend()
920 ds3000_writereg(state, 0x00, 0x01); in ds3000_set_frontend()
925 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) in ds3000_set_frontend()
929 value = ds3000_readreg(state, 0xfe); in ds3000_set_frontend()
930 value &= 0xc0; in ds3000_set_frontend()
931 value |= 0x1b; in ds3000_set_frontend()
932 ds3000_writereg(state, 0xfe, value); in ds3000_set_frontend()
936 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) in ds3000_set_frontend()
941 ds3000_writereg(state, 0xfe, 0x54); in ds3000_set_frontend()
943 ds3000_writereg(state, 0xfe, 0x98); in ds3000_set_frontend()
950 ds3000_writereg(state, 0x29, 0x80); in ds3000_set_frontend()
952 ds3000_writereg(state, 0x25, 0x8a); in ds3000_set_frontend()
966 if (value % 2 != 0) in ds3000_set_frontend()
968 ds3000_writereg(state, 0xc3, 0x0d); in ds3000_set_frontend()
969 ds3000_writereg(state, 0xc8, value); in ds3000_set_frontend()
970 ds3000_writereg(state, 0xc4, 0x10); in ds3000_set_frontend()
971 ds3000_writereg(state, 0xc7, 0x0e); in ds3000_set_frontend()
974 if (value % 2 != 0) in ds3000_set_frontend()
976 ds3000_writereg(state, 0xc3, 0x07); in ds3000_set_frontend()
977 ds3000_writereg(state, 0xc8, value); in ds3000_set_frontend()
978 ds3000_writereg(state, 0xc4, 0x09); in ds3000_set_frontend()
979 ds3000_writereg(state, 0xc7, 0x12); in ds3000_set_frontend()
982 ds3000_writereg(state, 0xc3, value); in ds3000_set_frontend()
983 ds3000_writereg(state, 0xc8, 0x0e); in ds3000_set_frontend()
984 ds3000_writereg(state, 0xc4, 0x07); in ds3000_set_frontend()
985 ds3000_writereg(state, 0xc7, 0x18); in ds3000_set_frontend()
988 ds3000_writereg(state, 0xc3, value); in ds3000_set_frontend()
989 ds3000_writereg(state, 0xc8, 0x0a); in ds3000_set_frontend()
990 ds3000_writereg(state, 0xc4, 0x05); in ds3000_set_frontend()
991 ds3000_writereg(state, 0xc7, 0x24); in ds3000_set_frontend()
997 ds3000_writereg(state, 0x61, value & 0x00ff); in ds3000_set_frontend()
998 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); in ds3000_set_frontend()
1001 ds3000_writereg(state, 0x56, 0x00); in ds3000_set_frontend()
1004 ds3000_writereg(state, 0x76, 0x00); in ds3000_set_frontend()
1006 /*ds3000_writereg(state, 0x08, 0x03); in ds3000_set_frontend()
1007 ds3000_writereg(state, 0xfd, 0x22); in ds3000_set_frontend()
1008 ds3000_writereg(state, 0x08, 0x07); in ds3000_set_frontend()
1009 ds3000_writereg(state, 0xfd, 0x42); in ds3000_set_frontend()
1010 ds3000_writereg(state, 0x08, 0x07);*/ in ds3000_set_frontend()
1016 ds3000_writereg(state, 0xfd, 0x80); in ds3000_set_frontend()
1019 ds3000_writereg(state, 0xfd, 0x01); in ds3000_set_frontend()
1025 ds3000_writereg(state, 0x00, 0x00); in ds3000_set_frontend()
1027 ds3000_writereg(state, 0xb2, 0x00); in ds3000_set_frontend()
1035 for (i = 0; i < 30 ; i++) { in ds3000_set_frontend()
1043 return 0; in ds3000_set_frontend()
1068 state->config->set_lock_led(fe, 0); in ds3000_get_algo()
1086 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); in ds3000_initfe()
1091 if (ret != 0) { in ds3000_initfe()
1096 return 0; in ds3000_initfe()
1137 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");