41 } while (0)
45 } while (0)
49 } while (0)
56 		.addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1  in itd1000_write_regs()
66 	buf[0] = reg;  in itd1000_write_regs()
69 	/* itd_dbg("wr %02x: %02x\n", reg, v[0]); */  in itd1000_write_regs()
75 	return 0;  in itd1000_write_regs()
82 		{ .addr = state->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },  in itd1000_read_reg()
87 	itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);  in itd1000_read_reg()
110 	{        0, 0x8, 0x3 },
111 	{  5200000, 0x8, 0x3 },
112 	{ 12200000, 0x4, 0x3 },
113 	{ 15400000, 0x2, 0x3 },
114 	{ 19800000, 0x2, 0x3 },
115 	{ 21500000, 0x2, 0x3 },
116 	{ 24500000, 0x2, 0x3 },
117 	{ 28400000, 0x2, 0x3 },
118 	{ 33400000, 0x2, 0x3 },
119 	{ 34400000, 0x1, 0x4 },
120 	{ 34400000, 0x1, 0x4 },
121 	{ 38400000, 0x1, 0x4 },
122 	{ 38400000, 0x1, 0x4 },
123 	{ 40400000, 0x1, 0x4 },
124 	{ 45400000, 0x1, 0x4 },
130 	u8 con1    = itd1000_read_reg(state, CON1)    & 0xfd;  in itd1000_set_lpf_bw()
131 	u8 pllfh   = itd1000_read_reg(state, PLLFH)   & 0x0f;  in itd1000_set_lpf_bw()
132 	u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;  in itd1000_set_lpf_bw()
133 	u8 bw      = itd1000_read_reg(state, BW)      & 0xf0;  in itd1000_set_lpf_bw()
140 	for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)  in itd1000_set_lpf_bw()
145 			itd1000_write_reg(state, BW,      bw | (i & 0x0f));  in itd1000_set_lpf_bw()
149 	itd1000_write_reg(state, CON1, con1 | (0 << 1));  in itd1000_set_lpf_bw()
176 	u8 gvbb_i2c     = itd1000_read_reg(state, GVBB_I2C) & 0xbf;  in itd1000_set_vco()
177 	u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;  in itd1000_set_vco()
183 	for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {  in itd1000_set_vco()
188 			adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;  in itd1000_set_vco()
208 	{ 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
209 	{ 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
210 	{ 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
211 	{ 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
212 	{ 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
213 	{ 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
214 	{ 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
215 	{ 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
216 	{ 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
217 	{ 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
242 	itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */  in itd1000_set_lo()
243 	itd1000_write_reg(state, PLLNL, plln & 0xff);  in itd1000_set_lo()
244 	itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));  in itd1000_set_lo()
245 	itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);  in itd1000_set_lo()
246 	itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);  in itd1000_set_lo()
248 	for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {  in itd1000_set_lo()
251 			itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);  in itd1000_set_lo()
252 			for (j = 0; j < 9; j++)  in itd1000_set_lo()
270 	pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;  in itd1000_set_parameters()
274 	return 0;  in itd1000_set_parameters()
281 	return 0;  in itd1000_get_frequency()
286 	return 0;  in itd1000_get_bandwidth()
290 	{ PLLCON1,       0x65 }, /* Register does not change */
291 	{ PLLNH,         0x80 }, /* Bits [7:6] do not change */
292 	{ RESERVED_0X6D, 0x3b },
293 	{ VCO_CHP2_I2C,  0x12 },
294 	{ 0x72,          0xf9 }, /* No such regsister defined */
295 	{ RESERVED_0X73, 0xff },
296 	{ RESERVED_0X74, 0xb2 },
297 	{ RESERVED_0X75, 0xc7 },
298 	{ EXTGVBBRF,     0xf0 },
299 	{ DIVAGCCK,      0x80 },
300 	{ BBTR,          0xa0 },
301 	{ RESERVED_0X7E, 0x4f },
302 	{ 0x82,          0x88 }, /* No such regsister defined */
303 	{ 0x83,          0x80 }, /* No such regsister defined */
304 	{ 0x84,          0x80 }, /* No such regsister defined */
305 	{ RESERVED_0X85, 0x74 },
306 	{ RESERVED_0X86, 0xff },
307 	{ RESERVED_0X88, 0x02 },
308 	{ RESERVED_0X89, 0x16 },
309 	{ RFST0,         0x1f },
310 	{ RESERVED_0X94, 0x66 },
311 	{ RESERVED_0X95, 0x66 },
312 	{ RESERVED_0X96, 0x77 },
313 	{ RESERVED_0X97, 0x99 },
314 	{ RESERVED_0X98, 0xff },
315 	{ RESERVED_0X99, 0xfc },
316 	{ RESERVED_0X9A, 0xba },
317 	{ RESERVED_0X9B, 0xaa },
321 	{ VCO_CHP1_I2C, 0x8a },
322 	{ BW,           0x87 },
323 	{ GVBB_I2C,     0x03 },
324 	{ BBGVMIN,      0x03 },
325 	{ CON1,         0x2e },
334 	for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)  in itd1000_init()
335 		itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);  in itd1000_init()
337 	for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)  in itd1000_init()
338 		itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);  in itd1000_init()
340 	return 0;  in itd1000_init()
345 	return 0;  in itd1000_sleep()
376 	u8 i = 0;  in itd1000_attach()
385 	i = itd1000_read_reg(state, 0);  in itd1000_attach()
386 	if (i != 0) {  in itd1000_attach()
392 	memset(state->shadow, 0xff, sizeof(state->shadow));  in itd1000_attach()
393 	for (i = 0x65; i < 0x9c; i++)  in itd1000_attach()