Lines Matching +full:0 +full:x35
255 {DVBT_DAGC_TRG_VAL, 0x39},
256 {DVBT_AGC_TARG_VAL_0, 0x0},
257 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
258 {DVBT_AAGC_LOOP_GAIN, 0x16},
259 {DVBT_LOOP_GAIN2_3_0, 0x6},
260 {DVBT_LOOP_GAIN2_4, 0x1},
261 {DVBT_LOOP_GAIN3, 0x16},
262 {DVBT_VTOP1, 0x35},
263 {DVBT_VTOP2, 0x21},
264 {DVBT_VTOP3, 0x21},
265 {DVBT_KRF1, 0x0},
266 {DVBT_KRF2, 0x40},
267 {DVBT_KRF3, 0x10},
268 {DVBT_KRF4, 0x10},
269 {DVBT_IF_AGC_MIN, 0x80},
270 {DVBT_IF_AGC_MAX, 0x7f},
271 {DVBT_RF_AGC_MIN, 0x9c},
272 {DVBT_RF_AGC_MAX, 0x7f},
273 {DVBT_POLAR_RF_AGC, 0x0},
274 {DVBT_POLAR_IF_AGC, 0x0},
275 {DVBT_AD7_SETTING, 0xe9f4},
279 {DVBT_DAGC_TRG_VAL, 0x39},
280 {DVBT_AGC_TARG_VAL_0, 0x0},
281 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
282 {DVBT_AAGC_LOOP_GAIN, 0x16},
283 {DVBT_LOOP_GAIN2_3_0, 0x6},
284 {DVBT_LOOP_GAIN2_4, 0x1},
285 {DVBT_LOOP_GAIN3, 0x16},
286 {DVBT_VTOP1, 0x35},
287 {DVBT_VTOP2, 0x21},
288 {DVBT_VTOP3, 0x21},
289 {DVBT_KRF1, 0x0},
290 {DVBT_KRF2, 0x40},
291 {DVBT_KRF3, 0x10},
292 {DVBT_KRF4, 0x10},
293 {DVBT_IF_AGC_MIN, 0x80},
294 {DVBT_IF_AGC_MAX, 0x7f},
295 {DVBT_RF_AGC_MIN, 0x9c},
296 {DVBT_RF_AGC_MAX, 0x7f},
297 {DVBT_POLAR_RF_AGC, 0x0},
298 {DVBT_POLAR_IF_AGC, 0x0},
299 {DVBT_AD7_SETTING, 0xe9f4},
300 {DVBT_OPT_ADC_IQ, 0x1},
301 {DVBT_AD_AVI, 0x0},
302 {DVBT_AD_AVQ, 0x0},
303 {DVBT_SPEC_INV, 0x0},
307 {DVBT_DAGC_TRG_VAL, 0x5a},
308 {DVBT_AGC_TARG_VAL_0, 0x0},
309 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
310 {DVBT_AAGC_LOOP_GAIN, 0x16},
311 {DVBT_LOOP_GAIN2_3_0, 0x6},
312 {DVBT_LOOP_GAIN2_4, 0x1},
313 {DVBT_LOOP_GAIN3, 0x16},
314 {DVBT_VTOP1, 0x35},
315 {DVBT_VTOP2, 0x21},
316 {DVBT_VTOP3, 0x21},
317 {DVBT_KRF1, 0x0},
318 {DVBT_KRF2, 0x40},
319 {DVBT_KRF3, 0x10},
320 {DVBT_KRF4, 0x10},
321 {DVBT_IF_AGC_MIN, 0x80},
322 {DVBT_IF_AGC_MAX, 0x7f},
323 {DVBT_RF_AGC_MIN, 0x80},
324 {DVBT_RF_AGC_MAX, 0x7f},
325 {DVBT_POLAR_RF_AGC, 0x0},
326 {DVBT_POLAR_IF_AGC, 0x0},
327 {DVBT_AD7_SETTING, 0xe9bf},
328 {DVBT_EN_GI_PGA, 0x0},
329 {DVBT_THD_LOCK_UP, 0x0},
330 {DVBT_THD_LOCK_DW, 0x0},
331 {DVBT_THD_UP1, 0x11},
332 {DVBT_THD_DW1, 0xef},
333 {DVBT_INTER_CNT_LEN, 0xc},
334 {DVBT_GI_PGA_STATE, 0x0},
335 {DVBT_EN_AGC_PGA, 0x1},
336 {DVBT_IF_AGC_MAN, 0x0},
337 {DVBT_SPEC_INV, 0x0},
341 {DVBT_DAGC_TRG_VAL, 0x5a},
342 {DVBT_AGC_TARG_VAL_0, 0x0},
343 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
344 {DVBT_AAGC_LOOP_GAIN, 0x18},
345 {DVBT_LOOP_GAIN2_3_0, 0x8},
346 {DVBT_LOOP_GAIN2_4, 0x1},
347 {DVBT_LOOP_GAIN3, 0x18},
348 {DVBT_VTOP1, 0x35},
349 {DVBT_VTOP2, 0x21},
350 {DVBT_VTOP3, 0x21},
351 {DVBT_KRF1, 0x0},
352 {DVBT_KRF2, 0x40},
353 {DVBT_KRF3, 0x10},
354 {DVBT_KRF4, 0x10},
355 {DVBT_IF_AGC_MIN, 0x80},
356 {DVBT_IF_AGC_MAX, 0x7f},
357 {DVBT_RF_AGC_MIN, 0x80},
358 {DVBT_RF_AGC_MAX, 0x7f},
359 {DVBT_POLAR_RF_AGC, 0x0},
360 {DVBT_POLAR_IF_AGC, 0x0},
361 {DVBT_AD7_SETTING, 0xe9d4},
362 {DVBT_EN_GI_PGA, 0x0},
363 {DVBT_THD_LOCK_UP, 0x0},
364 {DVBT_THD_LOCK_DW, 0x0},
365 {DVBT_THD_UP1, 0x14},
366 {DVBT_THD_DW1, 0xec},
367 {DVBT_INTER_CNT_LEN, 0xc},
368 {DVBT_GI_PGA_STATE, 0x0},
369 {DVBT_EN_AGC_PGA, 0x1},
370 {DVBT_REG_GPE, 0x1},
371 {DVBT_REG_GPO, 0x1},
372 {DVBT_REG_MONSEL, 0x1},
373 {DVBT_REG_MON, 0x1},
374 {DVBT_REG_4MSEL, 0x0},
375 {DVBT_SPEC_INV, 0x0},
379 {DVBT_DAGC_TRG_VAL, 0x39},
380 {DVBT_AGC_TARG_VAL_0, 0x0},
381 {DVBT_AGC_TARG_VAL_8_1, 0x40},
382 {DVBT_AAGC_LOOP_GAIN, 0x16},
383 {DVBT_LOOP_GAIN2_3_0, 0x8},
384 {DVBT_LOOP_GAIN2_4, 0x1},
385 {DVBT_LOOP_GAIN3, 0x18},
386 {DVBT_VTOP1, 0x35},
387 {DVBT_VTOP2, 0x21},
388 {DVBT_VTOP3, 0x21},
389 {DVBT_KRF1, 0x0},
390 {DVBT_KRF2, 0x40},
391 {DVBT_KRF3, 0x10},
392 {DVBT_KRF4, 0x10},
393 {DVBT_IF_AGC_MIN, 0x80},
394 {DVBT_IF_AGC_MAX, 0x7f},
395 {DVBT_RF_AGC_MIN, 0x80},
396 {DVBT_RF_AGC_MAX, 0x7f},
397 {DVBT_POLAR_RF_AGC, 0x0},
398 {DVBT_POLAR_IF_AGC, 0x0},
399 {DVBT_AD7_SETTING, 0xe9f4},
400 {DVBT_SPEC_INV, 0x1},
404 {DVBT_DAGC_TRG_VAL, 0x39},
405 {DVBT_AGC_TARG_VAL_0, 0x0},
406 {DVBT_AGC_TARG_VAL_8_1, 0x40},
407 {DVBT_AAGC_LOOP_GAIN, 0x16},
408 {DVBT_LOOP_GAIN2_3_0, 0x8},
409 {DVBT_LOOP_GAIN2_4, 0x1},
410 {DVBT_LOOP_GAIN3, 0x18},
411 {DVBT_VTOP1, 0x35},
412 {DVBT_VTOP2, 0x21},
413 {DVBT_VTOP3, 0x21},
414 {DVBT_KRF1, 0x0},
415 {DVBT_KRF2, 0x40},
416 {DVBT_KRF3, 0x10},
417 {DVBT_KRF4, 0x10},
418 {DVBT_IF_AGC_MIN, 0x80},
419 {DVBT_IF_AGC_MAX, 0x7f},
420 {DVBT_RF_AGC_MIN, 0x80},
421 {DVBT_RF_AGC_MAX, 0x7f},
422 {DVBT_POLAR_RF_AGC, 0x0},
423 {DVBT_POLAR_IF_AGC, 0x0},
424 {DVBT_AD7_SETTING, 0xe9f4},
425 {DVBT_SPEC_INV, 0x0},