Lines Matching +full:0 +full:x030
24 #define ISP_REVISION (0x000)
25 #define ISP_SYSCONFIG (0x004)
26 #define ISP_SYSSTATUS (0x008)
27 #define ISP_IRQ0ENABLE (0x00C)
28 #define ISP_IRQ0STATUS (0x010)
29 #define ISP_IRQ1ENABLE (0x014)
30 #define ISP_IRQ1STATUS (0x018)
31 #define ISP_TCTRL_GRESET_LENGTH (0x030)
32 #define ISP_TCTRL_PSTRB_REPLAY (0x034)
33 #define ISP_CTRL (0x040)
34 #define ISP_SECURE (0x044)
35 #define ISP_TCTRL_CTRL (0x050)
36 #define ISP_TCTRL_FRAME (0x054)
37 #define ISP_TCTRL_PSTRB_DELAY (0x058)
38 #define ISP_TCTRL_STRB_DELAY (0x05C)
39 #define ISP_TCTRL_SHUT_DELAY (0x060)
40 #define ISP_TCTRL_PSTRB_LENGTH (0x064)
41 #define ISP_TCTRL_STRB_LENGTH (0x068)
42 #define ISP_TCTRL_SHUT_LENGTH (0x06C)
43 #define ISP_PING_PONG_ADDR (0x070)
44 #define ISP_PING_PONG_MEM_RANGE (0x074)
45 #define ISP_PING_PONG_BUF_SIZE (0x078)
49 #define ISPCCP2_REVISION (0x000)
50 #define ISPCCP2_SYSCONFIG (0x004)
52 #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1
55 (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
57 (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
59 (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
60 #define ISPCCP2_SYSSTATUS (0x008)
61 #define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0)
62 #define ISPCCP2_LC01_IRQENABLE (0x00C)
63 #define ISPCCP2_LC01_IRQSTATUS (0x010)
74 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0)
76 #define ISPCCP2_LC23_IRQENABLE (0x014)
77 #define ISPCCP2_LC23_IRQSTATUS (0x018)
78 #define ISPCCP2_LCM_IRQENABLE (0x02C)
79 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0)
81 #define ISPCCP2_LCM_IRQSTATUS (0x030)
82 #define ISPCCP2_CTRL (0x040)
83 #define ISPCCP2_CTRL_IF_EN (1 << 0)
85 #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1)
87 #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
90 #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
95 #define ISPCCP2_CTRL_INV_MASK 0x1
99 #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
102 #define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
104 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK 0x3 /* 3430 bits */
105 #define ISPCCP2_DBG (0x044)
106 #define ISPCCP2_GNQ (0x048)
107 #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x))
108 #define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0)
110 #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1
114 #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1
116 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f
117 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0 0x2
118 #define ISPCCP2_LCx_CTRL_FORMAT_MASK 0x1f
119 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT 0x3
120 #define ISPCCP2_LCx_CODE(x) ((0x054)+0x30*(x))
121 #define ISPCCP2_LCx_STAT_START(x) ((0x058)+0x30*(x))
122 #define ISPCCP2_LCx_STAT_SIZE(x) ((0x05C)+0x30*(x))
123 #define ISPCCP2_LCx_SOF_ADDR(x) ((0x060)+0x30*(x))
124 #define ISPCCP2_LCx_EOF_ADDR(x) ((0x064)+0x30*(x))
125 #define ISPCCP2_LCx_DAT_START(x) ((0x068)+0x30*(x))
126 #define ISPCCP2_LCx_DAT_SIZE(x) ((0x06C)+0x30*(x))
127 #define ISPCCP2_LCx_DAT_MASK 0xFFF
129 #define ISPCCP2_LCx_DAT_PING_ADDR(x) ((0x070)+0x30*(x))
130 #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x))
131 #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x))
132 #define ISPCCP2_LCM_CTRL (0x1D0)
133 #define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0)
137 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11
139 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK 0x7
141 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7
143 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3
147 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7
148 #define ISPCCP2_LCM_VSIZE (0x1D4)
150 #define ISPCCP2_LCM_HSIZE (0x1D8)
152 #define ISPCCP2_LCM_PREFETCH (0x1DC)
154 #define ISPCCP2_LCM_SRC_ADDR (0x1E0)
155 #define ISPCCP2_LCM_SRC_OFST (0x1E4)
156 #define ISPCCP2_LCM_DST_ADDR (0x1E8)
157 #define ISPCCP2_LCM_DST_OFST (0x1EC)
161 #define ISPCCDC_PID (0x000)
162 #define ISPCCDC_PCR (0x004)
163 #define ISPCCDC_SYN_MODE (0x008)
164 #define ISPCCDC_HD_VD_WID (0x00C)
165 #define ISPCCDC_PIX_LINES (0x010)
166 #define ISPCCDC_HORZ_INFO (0x014)
167 #define ISPCCDC_VERT_START (0x018)
168 #define ISPCCDC_VERT_LINES (0x01C)
169 #define ISPCCDC_CULLING (0x020)
170 #define ISPCCDC_HSIZE_OFF (0x024)
171 #define ISPCCDC_SDOFST (0x028)
172 #define ISPCCDC_SDR_ADDR (0x02C)
173 #define ISPCCDC_CLAMP (0x030)
174 #define ISPCCDC_DCSUB (0x034)
175 #define ISPCCDC_COLPTN (0x038)
176 #define ISPCCDC_BLKCMP (0x03C)
177 #define ISPCCDC_FPC (0x040)
178 #define ISPCCDC_FPC_ADDR (0x044)
179 #define ISPCCDC_VDINT (0x048)
180 #define ISPCCDC_ALAW (0x04C)
181 #define ISPCCDC_REC656IF (0x050)
182 #define ISPCCDC_CFG (0x054)
183 #define ISPCCDC_FMTCFG (0x058)
184 #define ISPCCDC_FMT_HORZ (0x05C)
185 #define ISPCCDC_FMT_VERT (0x060)
186 #define ISPCCDC_FMT_ADDR0 (0x064)
187 #define ISPCCDC_FMT_ADDR1 (0x068)
188 #define ISPCCDC_FMT_ADDR2 (0x06C)
189 #define ISPCCDC_FMT_ADDR3 (0x070)
190 #define ISPCCDC_FMT_ADDR4 (0x074)
191 #define ISPCCDC_FMT_ADDR5 (0x078)
192 #define ISPCCDC_FMT_ADDR6 (0x07C)
193 #define ISPCCDC_FMT_ADDR7 (0x080)
194 #define ISPCCDC_PRGEVEN0 (0x084)
195 #define ISPCCDC_PRGEVEN1 (0x088)
196 #define ISPCCDC_PRGODD0 (0x08C)
197 #define ISPCCDC_PRGODD1 (0x090)
198 #define ISPCCDC_VP_OUT (0x094)
200 #define ISPCCDC_LSC_CONFIG (0x098)
201 #define ISPCCDC_LSC_INITIAL (0x09C)
202 #define ISPCCDC_LSC_TABLE_BASE (0x0A0)
203 #define ISPCCDC_LSC_TABLE_OFFSET (0x0A4)
206 #define ISPSBL_PCR 0x4
218 #define ISPSBL_CCDC_WR_0 (0x028)
220 #define ISPSBL_CCDC_WR_1 (0x02C)
221 #define ISPSBL_CCDC_WR_2 (0x030)
222 #define ISPSBL_CCDC_WR_3 (0x034)
224 #define ISPSBL_SDR_REQ_EXP 0xF8
225 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT 0
226 #define ISPSBL_SDR_REQ_HIST_EXP_MASK (0x3FF)
228 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
230 #define ISPSBL_SDR_REQ_PRV_EXP_MASK (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
233 #define ISPHIST_PID (0x000)
234 #define ISPHIST_PCR (0x004)
235 #define ISPHIST_CNT (0x008)
236 #define ISPHIST_WB_GAIN (0x00C)
237 #define ISPHIST_R0_HORZ (0x010)
238 #define ISPHIST_R0_VERT (0x014)
239 #define ISPHIST_R1_HORZ (0x018)
240 #define ISPHIST_R1_VERT (0x01C)
241 #define ISPHIST_R2_HORZ (0x020)
242 #define ISPHIST_R2_VERT (0x024)
243 #define ISPHIST_R3_HORZ (0x028)
244 #define ISPHIST_R3_VERT (0x02C)
245 #define ISPHIST_ADDR (0x030)
246 #define ISPHIST_DATA (0x034)
247 #define ISPHIST_RADD (0x038)
248 #define ISPHIST_RADD_OFF (0x03C)
249 #define ISPHIST_H_V_INFO (0x040)
252 #define ISPH3A_PID (0x000)
253 #define ISPH3A_PCR (0x004)
254 #define ISPH3A_AEWWIN1 (0x04C)
255 #define ISPH3A_AEWINSTART (0x050)
256 #define ISPH3A_AEWINBLK (0x054)
257 #define ISPH3A_AEWSUBWIN (0x058)
258 #define ISPH3A_AEWBUFST (0x05C)
259 #define ISPH3A_AFPAX1 (0x008)
260 #define ISPH3A_AFPAX2 (0x00C)
261 #define ISPH3A_AFPAXSTART (0x010)
262 #define ISPH3A_AFIIRSH (0x014)
263 #define ISPH3A_AFBUFST (0x018)
264 #define ISPH3A_AFCOEF010 (0x01C)
265 #define ISPH3A_AFCOEF032 (0x020)
266 #define ISPH3A_AFCOEF054 (0x024)
267 #define ISPH3A_AFCOEF076 (0x028)
268 #define ISPH3A_AFCOEF098 (0x02C)
269 #define ISPH3A_AFCOEF0010 (0x030)
270 #define ISPH3A_AFCOEF110 (0x034)
271 #define ISPH3A_AFCOEF132 (0x038)
272 #define ISPH3A_AFCOEF154 (0x03C)
273 #define ISPH3A_AFCOEF176 (0x040)
274 #define ISPH3A_AFCOEF198 (0x044)
275 #define ISPH3A_AFCOEF1010 (0x048)
277 #define ISPPRV_PCR (0x004)
278 #define ISPPRV_HORZ_INFO (0x008)
279 #define ISPPRV_VERT_INFO (0x00C)
280 #define ISPPRV_RSDR_ADDR (0x010)
281 #define ISPPRV_RADR_OFFSET (0x014)
282 #define ISPPRV_DSDR_ADDR (0x018)
283 #define ISPPRV_DRKF_OFFSET (0x01C)
284 #define ISPPRV_WSDR_ADDR (0x020)
285 #define ISPPRV_WADD_OFFSET (0x024)
286 #define ISPPRV_AVE (0x028)
287 #define ISPPRV_HMED (0x02C)
288 #define ISPPRV_NF (0x030)
289 #define ISPPRV_WB_DGAIN (0x034)
290 #define ISPPRV_WBGAIN (0x038)
291 #define ISPPRV_WBSEL (0x03C)
292 #define ISPPRV_CFA (0x040)
293 #define ISPPRV_BLKADJOFF (0x044)
294 #define ISPPRV_RGB_MAT1 (0x048)
295 #define ISPPRV_RGB_MAT2 (0x04C)
296 #define ISPPRV_RGB_MAT3 (0x050)
297 #define ISPPRV_RGB_MAT4 (0x054)
298 #define ISPPRV_RGB_MAT5 (0x058)
299 #define ISPPRV_RGB_OFF1 (0x05C)
300 #define ISPPRV_RGB_OFF2 (0x060)
301 #define ISPPRV_CSC0 (0x064)
302 #define ISPPRV_CSC1 (0x068)
303 #define ISPPRV_CSC2 (0x06C)
304 #define ISPPRV_CSC_OFFSET (0x070)
305 #define ISPPRV_CNT_BRT (0x074)
306 #define ISPPRV_CSUP (0x078)
307 #define ISPPRV_SETUP_YC (0x07C)
308 #define ISPPRV_SET_TBL_ADDR (0x080)
309 #define ISPPRV_SET_TBL_DATA (0x084)
310 #define ISPPRV_CDC_THR0 (0x090)
311 #define ISPPRV_CDC_THR1 (ISPPRV_CDC_THR0 + (0x4))
312 #define ISPPRV_CDC_THR2 (ISPPRV_CDC_THR0 + (0x4) * 2)
313 #define ISPPRV_CDC_THR3 (ISPPRV_CDC_THR0 + (0x4) * 3)
315 #define ISPPRV_REDGAMMA_TABLE_ADDR 0x0000
316 #define ISPPRV_GREENGAMMA_TABLE_ADDR 0x0400
317 #define ISPPRV_BLUEGAMMA_TABLE_ADDR 0x0800
318 #define ISPPRV_NF_TABLE_ADDR 0x0C00
319 #define ISPPRV_YENH_TABLE_ADDR 0x1000
320 #define ISPPRV_CFA_TABLE_ADDR 0x1400
326 #define ISPRSZ_PID (0x000)
327 #define ISPRSZ_PCR (0x004)
328 #define ISPRSZ_CNT (0x008)
329 #define ISPRSZ_OUT_SIZE (0x00C)
330 #define ISPRSZ_IN_START (0x010)
331 #define ISPRSZ_IN_SIZE (0x014)
332 #define ISPRSZ_SDR_INADD (0x018)
333 #define ISPRSZ_SDR_INOFF (0x01C)
334 #define ISPRSZ_SDR_OUTADD (0x020)
335 #define ISPRSZ_SDR_OUTOFF (0x024)
336 #define ISPRSZ_HFILT10 (0x028)
337 #define ISPRSZ_HFILT32 (0x02C)
338 #define ISPRSZ_HFILT54 (0x030)
339 #define ISPRSZ_HFILT76 (0x034)
340 #define ISPRSZ_HFILT98 (0x038)
341 #define ISPRSZ_HFILT1110 (0x03C)
342 #define ISPRSZ_HFILT1312 (0x040)
343 #define ISPRSZ_HFILT1514 (0x044)
344 #define ISPRSZ_HFILT1716 (0x048)
345 #define ISPRSZ_HFILT1918 (0x04C)
346 #define ISPRSZ_HFILT2120 (0x050)
347 #define ISPRSZ_HFILT2322 (0x054)
348 #define ISPRSZ_HFILT2524 (0x058)
349 #define ISPRSZ_HFILT2726 (0x05C)
350 #define ISPRSZ_HFILT2928 (0x060)
351 #define ISPRSZ_HFILT3130 (0x064)
352 #define ISPRSZ_VFILT10 (0x068)
353 #define ISPRSZ_VFILT32 (0x06C)
354 #define ISPRSZ_VFILT54 (0x070)
355 #define ISPRSZ_VFILT76 (0x074)
356 #define ISPRSZ_VFILT98 (0x078)
357 #define ISPRSZ_VFILT1110 (0x07C)
358 #define ISPRSZ_VFILT1312 (0x080)
359 #define ISPRSZ_VFILT1514 (0x084)
360 #define ISPRSZ_VFILT1716 (0x088)
361 #define ISPRSZ_VFILT1918 (0x08C)
362 #define ISPRSZ_VFILT2120 (0x090)
363 #define ISPRSZ_VFILT2322 (0x094)
364 #define ISPRSZ_VFILT2524 (0x098)
365 #define ISPRSZ_VFILT2726 (0x09C)
366 #define ISPRSZ_VFILT2928 (0x0A0)
367 #define ISPRSZ_VFILT3130 (0x0A4)
368 #define ISPRSZ_YENH (0x0A8)
370 #define ISP_INT_CLR 0xFF113F11
383 #define ISPPRV_PCR_CFAFMT_MASK 0x7800
384 #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11)
393 #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17)
407 #define ISPPRV_HORZ_INFO_EPH_SHIFT 0
408 #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff
410 #define ISPPRV_HORZ_INFO_SPH_MASK 0x3fff0
412 #define ISPPRV_VERT_INFO_ELV_SHIFT 0
413 #define ISPPRV_VERT_INFO_ELV_MASK 0x3fff
415 #define ISPPRV_VERT_INFO_SLV_MASK 0x3fff0
418 #define ISPPRV_AVE_EVENDIST_1 0x0
419 #define ISPPRV_AVE_EVENDIST_2 0x1
420 #define ISPPRV_AVE_EVENDIST_3 0x2
421 #define ISPPRV_AVE_EVENDIST_4 0x3
423 #define ISPPRV_AVE_ODDDIST_1 0x0
424 #define ISPPRV_AVE_ODDDIST_2 0x1
425 #define ISPPRV_AVE_ODDDIST_3 0x2
426 #define ISPPRV_AVE_ODDDIST_4 0x3
428 #define ISPPRV_HMED_THRESHOLD_SHIFT 0
432 #define ISPPRV_WBGAIN_COEF0_SHIFT 0
437 #define ISPPRV_WBSEL_COEF0 0x0
438 #define ISPPRV_WBSEL_COEF1 0x1
439 #define ISPPRV_WBSEL_COEF2 0x2
440 #define ISPPRV_WBSEL_COEF3 0x3
442 #define ISPPRV_WBSEL_N0_0_SHIFT 0
459 #define ISPPRV_CFA_GRADTH_HOR_SHIFT 0
462 #define ISPPRV_BLKADJOFF_B_SHIFT 0
466 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT 0
469 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT 0
472 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT 0
475 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT 0
478 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT 0
480 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT 0
483 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT 0
485 #define ISPPRV_CSC0_RY_SHIFT 0
489 #define ISPPRV_CSC1_RCB_SHIFT 0
493 #define ISPPRV_CSC2_RCR_SHIFT 0
497 #define ISPPRV_CSC_OFFSET_CR_SHIFT 0
501 #define ISPPRV_CNT_BRT_BRT_SHIFT 0
504 #define ISPPRV_CONTRAST_MAX 0x10
505 #define ISPPRV_CONTRAST_MIN 0xFF
506 #define ISPPRV_BRIGHT_MIN 0x00
507 #define ISPPRV_BRIGHT_MAX 0xFF
509 #define ISPPRV_CSUP_CSUPG_SHIFT 0
513 #define ISPPRV_SETUP_YC_MINC_SHIFT 0
517 #define ISPPRV_YC_MAX 0xFF
518 #define ISPPRV_YC_MIN 0x0
521 #define ISP_REVISION_SHIFT 0
523 #define ISP_SYSCONFIG_AUTOIDLE (1 << 0)
526 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0
527 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1
528 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x2
530 #define ISP_SYSSTATUS_RESETDONE 0
532 #define IRQ0ENABLE_CSIA_IRQ (1 << 0)
565 #define IRQ0STATUS_CSIA_IRQ (1 << 0)
595 #define TCTRL_GRESET_LEN 0
597 #define TCTRL_PSTRB_REPLAY_DELAY 0
600 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL 0x0
601 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA 0x1
602 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB 0x2
603 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC 0x3
604 #define ISPCTRL_PAR_SER_CLK_SEL_MASK 0x3
607 #define ISPCTRL_PAR_BRIDGE_DISABLE (0x0 << 2)
608 #define ISPCTRL_PAR_BRIDGE_LENDIAN (0x2 << 2)
609 #define ISPCTRL_PAR_BRIDGE_BENDIAN (0x3 << 2)
610 #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2)
616 #define ISPCTRL_SHIFT_0 (0x0 << 6)
617 #define ISPCTRL_SHIFT_2 (0x1 << 6)
618 #define ISPCTRL_SHIFT_4 (0x2 << 6)
619 #define ISPCTRL_SHIFT_MASK (0x3 << 6)
628 #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
629 #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
630 #define ISPCTRL_SYNC_DETECT_VSFALL (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
631 #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
632 #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
646 #define ISPSECURE_SECUREMODE 0
648 #define ISPTCTRL_CTRL_DIV_LOW 0x0
649 #define ISPTCTRL_CTRL_DIV_HIGH 0x1
650 #define ISPTCTRL_CTRL_DIV_BYPASS 0x1F
652 #define ISPTCTRL_CTRL_DIVA_SHIFT 0
653 #define ISPTCTRL_CTRL_DIVA_MASK (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
656 #define ISPTCTRL_CTRL_DIVB_MASK (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
659 #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10)
668 #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27)
669 #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27)
670 #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27)
676 #define ISPTCTRL_FRAME_SHUT_SHIFT 0
680 #define ISPCCDC_PID_PREV_SHIFT 0
687 #define ISPCCDC_SYN_MODE_VDHDOUT 0x1
695 #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8)
696 #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8)
697 #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8)
698 #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8)
699 #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8)
700 #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8)
703 #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12)
713 #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0
716 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT 0
719 #define ISPCCDC_HORZ_INFO_NPH_SHIFT 0
720 #define ISPCCDC_HORZ_INFO_NPH_MASK 0x00007fff
722 #define ISPCCDC_HORZ_INFO_SPH_MASK 0x7fff0000
724 #define ISPCCDC_VERT_START_SLV1_SHIFT 0
726 #define ISPCCDC_VERT_START_SLV0_MASK 0x7fff0000
728 #define ISPCCDC_VERT_LINES_NLV_SHIFT 0
729 #define ISPCCDC_VERT_LINES_NLV_MASK 0x00007fff
731 #define ISPCCDC_CULLING_CULV_SHIFT 0
735 #define ISPCCDC_HSIZE_OFF_SHIFT 0
740 #define ISPCCDC_SDOFST_LOFST3_SHIFT 0
745 #define ISPCCDC_CLAMP_OBGAIN_SHIFT 0
751 #define ISPCCDC_COLPTN_R_Ye 0x0
752 #define ISPCCDC_COLPTN_Gr_Cy 0x1
753 #define ISPCCDC_COLPTN_Gb_G 0x2
754 #define ISPCCDC_COLPTN_B_Mg 0x3
755 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT 0
772 #define ISPCCDC_BLKCMP_B_MG_SHIFT 0
777 #define ISPCCDC_FPC_FPNUM_SHIFT 0
781 #define ISPCCDC_VDINT_1_SHIFT 0
782 #define ISPCCDC_VDINT_1_MASK 0x00007fff
784 #define ISPCCDC_VDINT_0_MASK 0x7fff0000
786 #define ISPCCDC_ALAW_GWDI_12_3 (0x3 << 0)
787 #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0)
788 #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0)
789 #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0)
798 #define ISPCCDC_CFG_WENLOG_AND (0 << 8)
805 #define ISPCCDC_FMTCFG_FMTEN 0x1
810 #define ISPCCDC_FMTCFG_VPIN_MASK 0x00007000
811 #define ISPCCDC_FMTCFG_VPIN_12_3 (0x3 << 12)
812 #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12)
813 #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12)
814 #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12)
817 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000
819 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2 (0x0 << 16)
820 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3 (0x1 << 16)
821 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4 (0x2 << 16)
822 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5 (0x3 << 16)
823 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6 (0x4 << 16)
825 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT 0
828 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT 0
831 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK 0x1fff0000
832 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK 0x00001fff
834 #define ISPCCDC_FMT_VERT_FMTSLV_MASK 0x1fff0000
835 #define ISPCCDC_FMT_VERT_FMTLNV_MASK 0x00001fff
837 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT 0
841 #define ISPRSZ_PID_PREV_SHIFT 0
845 #define ISPRSZ_PCR_ENABLE (1 << 0)
849 #define ISPRSZ_CNT_HRSZ_SHIFT 0
851 (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
854 (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
856 #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
858 #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
864 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0
866 (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
869 (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
871 #define ISPRSZ_IN_START_HORZ_ST_SHIFT 0
873 (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
876 (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
878 #define ISPRSZ_IN_SIZE_HORZ_SHIFT 0
880 (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
883 (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
885 #define ISPRSZ_SDR_INADD_ADDR_SHIFT 0
886 #define ISPRSZ_SDR_INADD_ADDR_MASK 0xFFFFFFFF
888 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT 0
890 (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
892 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT 0
893 #define ISPRSZ_SDR_OUTADD_ADDR_MASK 0xFFFFFFFF
896 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT 0
898 (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
900 #define ISPRSZ_HFILT_COEF0_SHIFT 0
902 (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
905 (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
907 #define ISPRSZ_HFILT32_COEF2_SHIFT 0
908 #define ISPRSZ_HFILT32_COEF2_MASK 0x3FF
910 #define ISPRSZ_HFILT32_COEF3_MASK 0x3FF0000
912 #define ISPRSZ_HFILT54_COEF4_SHIFT 0
913 #define ISPRSZ_HFILT54_COEF4_MASK 0x3FF
915 #define ISPRSZ_HFILT54_COEF5_MASK 0x3FF0000
917 #define ISPRSZ_HFILT76_COEFF6_SHIFT 0
918 #define ISPRSZ_HFILT76_COEFF6_MASK 0x3FF
920 #define ISPRSZ_HFILT76_COEFF7_MASK 0x3FF0000
922 #define ISPRSZ_HFILT98_COEFF8_SHIFT 0
923 #define ISPRSZ_HFILT98_COEFF8_MASK 0x3FF
925 #define ISPRSZ_HFILT98_COEFF9_MASK 0x3FF0000
927 #define ISPRSZ_HFILT1110_COEF10_SHIFT 0
928 #define ISPRSZ_HFILT1110_COEF10_MASK 0x3FF
930 #define ISPRSZ_HFILT1110_COEF11_MASK 0x3FF0000
932 #define ISPRSZ_HFILT1312_COEFF12_SHIFT 0
933 #define ISPRSZ_HFILT1312_COEFF12_MASK 0x3FF
935 #define ISPRSZ_HFILT1312_COEFF13_MASK 0x3FF0000
937 #define ISPRSZ_HFILT1514_COEFF14_SHIFT 0
938 #define ISPRSZ_HFILT1514_COEFF14_MASK 0x3FF
940 #define ISPRSZ_HFILT1514_COEFF15_MASK 0x3FF0000
942 #define ISPRSZ_HFILT1716_COEF16_SHIFT 0
943 #define ISPRSZ_HFILT1716_COEF16_MASK 0x3FF
945 #define ISPRSZ_HFILT1716_COEF17_MASK 0x3FF0000
947 #define ISPRSZ_HFILT1918_COEF18_SHIFT 0
948 #define ISPRSZ_HFILT1918_COEF18_MASK 0x3FF
950 #define ISPRSZ_HFILT1918_COEF19_MASK 0x3FF0000
952 #define ISPRSZ_HFILT2120_COEF20_SHIFT 0
953 #define ISPRSZ_HFILT2120_COEF20_MASK 0x3FF
955 #define ISPRSZ_HFILT2120_COEF21_MASK 0x3FF0000
957 #define ISPRSZ_HFILT2322_COEF22_SHIFT 0
958 #define ISPRSZ_HFILT2322_COEF22_MASK 0x3FF
960 #define ISPRSZ_HFILT2322_COEF23_MASK 0x3FF0000
962 #define ISPRSZ_HFILT2524_COEF24_SHIFT 0
963 #define ISPRSZ_HFILT2524_COEF24_MASK 0x3FF
965 #define ISPRSZ_HFILT2524_COEF25_MASK 0x3FF0000
967 #define ISPRSZ_HFILT2726_COEF26_SHIFT 0
968 #define ISPRSZ_HFILT2726_COEF26_MASK 0x3FF
970 #define ISPRSZ_HFILT2726_COEF27_MASK 0x3FF0000
972 #define ISPRSZ_HFILT2928_COEF28_SHIFT 0
973 #define ISPRSZ_HFILT2928_COEF28_MASK 0x3FF
975 #define ISPRSZ_HFILT2928_COEF29_MASK 0x3FF0000
977 #define ISPRSZ_HFILT3130_COEF30_SHIFT 0
978 #define ISPRSZ_HFILT3130_COEF30_MASK 0x3FF
980 #define ISPRSZ_HFILT3130_COEF31_MASK 0x3FF0000
982 #define ISPRSZ_VFILT_COEF0_SHIFT 0
984 (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
987 (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
989 #define ISPRSZ_VFILT10_COEF0_SHIFT 0
990 #define ISPRSZ_VFILT10_COEF0_MASK 0x3FF
992 #define ISPRSZ_VFILT10_COEF1_MASK 0x3FF0000
994 #define ISPRSZ_VFILT32_COEF2_SHIFT 0
995 #define ISPRSZ_VFILT32_COEF2_MASK 0x3FF
997 #define ISPRSZ_VFILT32_COEF3_MASK 0x3FF0000
999 #define ISPRSZ_VFILT54_COEF4_SHIFT 0
1000 #define ISPRSZ_VFILT54_COEF4_MASK 0x3FF
1002 #define ISPRSZ_VFILT54_COEF5_MASK 0x3FF0000
1004 #define ISPRSZ_VFILT76_COEFF6_SHIFT 0
1005 #define ISPRSZ_VFILT76_COEFF6_MASK 0x3FF
1007 #define ISPRSZ_VFILT76_COEFF7_MASK 0x3FF0000
1009 #define ISPRSZ_VFILT98_COEFF8_SHIFT 0
1010 #define ISPRSZ_VFILT98_COEFF8_MASK 0x3FF
1012 #define ISPRSZ_VFILT98_COEFF9_MASK 0x3FF0000
1014 #define ISPRSZ_VFILT1110_COEF10_SHIFT 0
1015 #define ISPRSZ_VFILT1110_COEF10_MASK 0x3FF
1017 #define ISPRSZ_VFILT1110_COEF11_MASK 0x3FF0000
1019 #define ISPRSZ_VFILT1312_COEFF12_SHIFT 0
1020 #define ISPRSZ_VFILT1312_COEFF12_MASK 0x3FF
1022 #define ISPRSZ_VFILT1312_COEFF13_MASK 0x3FF0000
1024 #define ISPRSZ_VFILT1514_COEFF14_SHIFT 0
1025 #define ISPRSZ_VFILT1514_COEFF14_MASK 0x3FF
1027 #define ISPRSZ_VFILT1514_COEFF15_MASK 0x3FF0000
1029 #define ISPRSZ_VFILT1716_COEF16_SHIFT 0
1030 #define ISPRSZ_VFILT1716_COEF16_MASK 0x3FF
1032 #define ISPRSZ_VFILT1716_COEF17_MASK 0x3FF0000
1034 #define ISPRSZ_VFILT1918_COEF18_SHIFT 0
1035 #define ISPRSZ_VFILT1918_COEF18_MASK 0x3FF
1037 #define ISPRSZ_VFILT1918_COEF19_MASK 0x3FF0000
1039 #define ISPRSZ_VFILT2120_COEF20_SHIFT 0
1040 #define ISPRSZ_VFILT2120_COEF20_MASK 0x3FF
1042 #define ISPRSZ_VFILT2120_COEF21_MASK 0x3FF0000
1044 #define ISPRSZ_VFILT2322_COEF22_SHIFT 0
1045 #define ISPRSZ_VFILT2322_COEF22_MASK 0x3FF
1047 #define ISPRSZ_VFILT2322_COEF23_MASK 0x3FF0000
1049 #define ISPRSZ_VFILT2524_COEF24_SHIFT 0
1050 #define ISPRSZ_VFILT2524_COEF24_MASK 0x3FF
1052 #define ISPRSZ_VFILT2524_COEF25_MASK 0x3FF0000
1054 #define ISPRSZ_VFILT2726_COEF26_SHIFT 0
1055 #define ISPRSZ_VFILT2726_COEF26_MASK 0x3FF
1057 #define ISPRSZ_VFILT2726_COEF27_MASK 0x3FF0000
1059 #define ISPRSZ_VFILT2928_COEF28_SHIFT 0
1060 #define ISPRSZ_VFILT2928_COEF28_MASK 0x3FF
1062 #define ISPRSZ_VFILT2928_COEF29_MASK 0x3FF0000
1064 #define ISPRSZ_VFILT3130_COEF30_SHIFT 0
1065 #define ISPRSZ_VFILT3130_COEF30_MASK 0x3FF
1067 #define ISPRSZ_VFILT3130_COEF31_MASK 0x3FF0000
1069 #define ISPRSZ_YENH_CORE_SHIFT 0
1071 (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1074 (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1077 (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1080 (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1086 #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000
1090 #define ISPH3A_AEWWIN1_WINHC_SHIFT 0
1091 #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F
1093 #define ISPH3A_AEWWIN1_WINVC_MASK 0x1FC0
1095 #define ISPH3A_AEWWIN1_WINW_MASK 0xFE000
1097 #define ISPH3A_AEWWIN1_WINH_MASK 0x7F000000
1099 #define ISPH3A_AEWINSTART_WINSH_SHIFT 0
1100 #define ISPH3A_AEWINSTART_WINSH_MASK 0x0FFF
1102 #define ISPH3A_AEWINSTART_WINSV_MASK 0x0FFF0000
1104 #define ISPH3A_AEWINBLK_WINH_SHIFT 0
1105 #define ISPH3A_AEWINBLK_WINH_MASK 0x7F
1107 #define ISPH3A_AEWINBLK_WINSV_MASK 0x0FFF0000
1109 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT 0
1110 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK 0x0F
1112 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK 0x0F00
1114 #define ISPHIST_PCR_ENABLE_SHIFT 0
1115 #define ISPHIST_PCR_ENABLE_MASK 0x01
1117 #define ISPHIST_PCR_BUSY 0x02
1120 #define ISPHIST_CNT_DATASIZE_MASK 0x0100
1122 #define ISPHIST_CNT_CLEAR_MASK 0x080
1125 #define ISPHIST_CNT_CFA_MASK 0x040
1127 #define ISPHIST_CNT_BINS_MASK 0x030
1129 #define ISPHIST_CNT_SOURCE_MASK 0x08
1130 #define ISPHIST_CNT_SHIFT_SHIFT 0
1131 #define ISPHIST_CNT_SHIFT_MASK 0x07
1134 #define ISPHIST_WB_GAIN_WG00_MASK 0xFF000000
1136 #define ISPHIST_WB_GAIN_WG01_MASK 0xFF0000
1138 #define ISPHIST_WB_GAIN_WG02_MASK 0xFF00
1139 #define ISPHIST_WB_GAIN_WG03_SHIFT 0
1140 #define ISPHIST_WB_GAIN_WG03_MASK 0xFF
1142 #define ISPHIST_REG_START_END_MASK 0x3FFF
1144 #define ISPHIST_REG_END_SHIFT 0
1153 #define ISPHIST_ADDR_SHIFT 0
1154 #define ISPHIST_ADDR_MASK 0x3FF
1156 #define ISPHIST_DATA_SHIFT 0
1157 #define ISPHIST_DATA_MASK 0xFFFFF
1159 #define ISPHIST_RADD_SHIFT 0
1160 #define ISPHIST_RADD_MASK 0xFFFFFFFF
1162 #define ISPHIST_RADD_OFF_SHIFT 0
1163 #define ISPHIST_RADD_OFF_MASK 0xFFFF
1166 #define ISPHIST_HV_INFO_HSIZE_MASK 0x3FFF0000
1167 #define ISPHIST_HV_INFO_VSIZE_SHIFT 0
1168 #define ISPHIST_HV_INFO_VSIZE_MASK 0x3FFF
1170 #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF
1174 #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700
1176 #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800
1178 #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE
1182 #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F
1183 #define ISPCCDC_LSC_INITIAL_X_SHIFT 0
1184 #define ISPCCDC_LSC_INITIAL_Y_MASK 0x3F0000
1188 * CSI2 receiver registers (ES2.0)
1191 #define ISPCSI2_REVISION (0x000)
1192 #define ISPCSI2_SYSCONFIG (0x010)
1195 (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1197 (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1199 (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1201 (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1203 #define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0)
1205 #define ISPCSI2_SYSSTATUS (0x014)
1206 #define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0)
1208 #define ISPCSI2_IRQSTATUS (0x018)
1218 #define ISPCSI2_IRQENABLE (0x01c)
1219 #define ISPCSI2_CTRL (0x040)
1232 #define ISPCSI2_CTRL_IF_EN (1 << 0)
1234 #define ISPCSI2_DBG_H (0x044)
1235 #define ISPCSI2_GNQ (0x048)
1236 #define ISPCSI2_PHY_CFG (0x050)
1241 (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1243 (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1245 (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1247 (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1250 (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1252 (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1254 (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1256 (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1261 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1263 (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1265 (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1269 (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1271 (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1273 (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1275 (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1277 (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1279 (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1281 (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1285 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1287 (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1289 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1291 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT 0
1293 (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1295 (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1297 (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1299 (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1301 (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1303 (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1305 #define ISPCSI2_PHY_IRQSTATUS (0x054)
1334 #define ISPCSI2_SHORT_PACKET (0x05c)
1335 #define ISPCSI2_PHY_IRQENABLE (0x060)
1362 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0)
1364 #define ISPCSI2_DBG_P (0x068)
1365 #define ISPCSI2_TIMING (0x06c)
1371 (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1373 #define ISPCSI2_CTX_CTRL1(n) ((0x070) + 0x20 * (n))
1376 (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1382 #define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0)
1384 #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n))
1387 (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1390 (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1392 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0
1394 (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1397 (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1399 #define ISPCSI2_CTX_DAT_OFST(n) ((0x078) + 0x20 * (n))
1400 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT 0
1402 (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1404 #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n))
1405 #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n))
1406 #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n))
1414 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0)
1416 #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n))
1424 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0)
1426 #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n))
1429 (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1432 #define ISPCSI2_CTX_TRANSCODEH(n) (0x000 + 0x8 * (n))
1435 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1436 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT 0
1438 (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1439 #define ISPCSI2_CTX_TRANSCODEV(n) (0x004 + 0x8 * (n))
1442 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1443 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT 0
1445 (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1451 #define ISPCSIPHY_REG0 (0x000)
1454 (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1455 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT 0
1457 (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1459 #define ISPCSIPHY_REG1 (0x004)
1465 (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1468 (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1472 (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1476 (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1477 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT 0
1479 (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1482 #define ISPCSIPHY_REG2 (0x008)
1485 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1488 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1491 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1494 (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1495 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT 0
1497 (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1512 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT 0
1513 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY 0x0
1514 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE 0x1
1515 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK 0x2
1516 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3
1517 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3