2  * Driver for Mediatek IR Receiver Controller
26 /* Register to enable PWM and IR */
29 /* Bit to enable IR pulse width detection */
34  * indicating IR receiving completion and then making IRQ fires
38 /* Bit to enable IR hardware function */
41 /* Bit to restart IR receiving */
47 /* IR threshold */
60 /* Indicate the end of IR message */
79 	/* Register to enable IR interrupt */
81 	/* Register to ack IR interrupt */
111  * @ok_count:		The count indicating the completion of IR data
140  * @clk:		The clock that IR internal is using
154 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)  in mtk_chkdata_reg()  argument
156 	return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;  in mtk_chkdata_reg()
159 static inline u32 mtk_chk_period(struct mtk_ir *ir)  in mtk_chk_period()  argument
165 				clk_get_rate(ir->bus) / ir->data->div);  in mtk_chk_period()
173 	dev_dbg(ir->dev, "@pwm clk  = \t%lu\n",  in mtk_chk_period()
174 		clk_get_rate(ir->bus) / ir->data->div);  in mtk_chk_period()
175 	dev_dbg(ir->dev, "@chkperiod = %08x\n", val);  in mtk_chk_period()
180 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)  in mtk_w32_mask()  argument
184 	tmp = __raw_readl(ir->base + reg);  in mtk_w32_mask()
186 	__raw_writel(tmp, ir->base + reg);  in mtk_w32_mask()
189 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)  in mtk_w32()  argument
191 	__raw_writel(val, ir->base + reg);  in mtk_w32()
194 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)  in mtk_r32()  argument
196 	return __raw_readl(ir->base + reg);  in mtk_r32()
199 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)  in mtk_irq_disable()  argument
203 	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);  in mtk_irq_disable()
204 	mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);  in mtk_irq_disable()
207 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)  in mtk_irq_enable()  argument
211 	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);  in mtk_irq_enable()
212 	mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);  in mtk_irq_enable()
217 	struct mtk_ir *ir = dev_id;  in mtk_ir_irq()  local
224 	 * because 1) the longest duration for space MTK IR hardware  in mtk_ir_irq()
229 	 * start of IR message is always contained in and starting  in mtk_ir_irq()
230 	 * from register mtk_chkdata_reg(ir, i).  in mtk_ir_irq()
232 	ir_raw_event_reset(ir->rc);  in mtk_ir_irq()
237 	/* Handle all pulse and space IR controller captures */  in mtk_ir_irq()
239 		val = mtk_r32(ir, mtk_chkdata_reg(ir, i));  in mtk_ir_irq()
240 		dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);  in mtk_ir_irq()
246 			ir_raw_event_store_with_filter(ir->rc, &rawir);  in mtk_ir_irq()
251 	 * The maximum number of edges the IR controller can  in mtk_ir_irq()
252 	 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages  in mtk_ir_irq()
253 	 * is over the limit, the last incomplete IR message would  in mtk_ir_irq()
255 	 * ir-rc-raw to decode. That helps it is possible that it  in mtk_ir_irq()
262 		ir_raw_event_store_with_filter(ir->rc, &rawir);  in mtk_ir_irq()
265 	ir_raw_event_handle(ir->rc);  in mtk_ir_irq()
271 	mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);  in mtk_ir_irq()
274 	mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,  in mtk_ir_irq()
275 		     ir->data->regs[MTK_IRINT_CLR_REG]);  in mtk_ir_irq()
308 	struct mtk_ir *ir;  in mtk_ir_probe()  local
313 	ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);  in mtk_ir_probe()
314 	if (!ir)  in mtk_ir_probe()
317 	ir->dev = dev;  in mtk_ir_probe()
318 	ir->data = of_device_get_match_data(dev);  in mtk_ir_probe()
320 	ir->clk = devm_clk_get(dev, "clk");  in mtk_ir_probe()
321 	if (IS_ERR(ir->clk)) {  in mtk_ir_probe()
322 		dev_err(dev, "failed to get a ir clock.\n");  in mtk_ir_probe()
323 		return PTR_ERR(ir->clk);  in mtk_ir_probe()
326 	ir->bus = devm_clk_get(dev, "bus");  in mtk_ir_probe()
327 	if (IS_ERR(ir->bus)) {  in mtk_ir_probe()
330 		 * ir->bus uses the same clock as ir->clock.  in mtk_ir_probe()
332 		ir->bus = ir->clk;  in mtk_ir_probe()
336 	ir->base = devm_ioremap_resource(dev, res);  in mtk_ir_probe()
337 	if (IS_ERR(ir->base)) {  in mtk_ir_probe()
339 		return PTR_ERR(ir->base);  in mtk_ir_probe()
342 	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);  in mtk_ir_probe()
343 	if (!ir->rc) {  in mtk_ir_probe()
348 	ir->rc->priv = ir;  in mtk_ir_probe()
349 	ir->rc->device_name = MTK_IR_DEV;  in mtk_ir_probe()
350 	ir->rc->input_phys = MTK_IR_DEV "/input0";  in mtk_ir_probe()
351 	ir->rc->input_id.bustype = BUS_HOST;  in mtk_ir_probe()
352 	ir->rc->input_id.vendor = 0x0001;  in mtk_ir_probe()
353 	ir->rc->input_id.product = 0x0001;  in mtk_ir_probe()
354 	ir->rc->input_id.version = 0x0001;  in mtk_ir_probe()
356 	ir->rc->map_name = map_name ?: RC_MAP_EMPTY;  in mtk_ir_probe()
357 	ir->rc->dev.parent = dev;  in mtk_ir_probe()
358 	ir->rc->driver_name = MTK_IR_DEV;  in mtk_ir_probe()
359 	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL;  in mtk_ir_probe()
360 	ir->rc->rx_resolution = MTK_IR_SAMPLE;  in mtk_ir_probe()
361 	ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);  in mtk_ir_probe()
363 	ret = devm_rc_register_device(dev, ir->rc);  in mtk_ir_probe()
369 	platform_set_drvdata(pdev, ir);  in mtk_ir_probe()
371 	ir->irq = platform_get_irq(pdev, 0);  in mtk_ir_probe()
372 	if (ir->irq < 0) {  in mtk_ir_probe()
377 	if (clk_prepare_enable(ir->clk)) {  in mtk_ir_probe()
382 	if (clk_prepare_enable(ir->bus)) {  in mtk_ir_probe()
392 	mtk_irq_disable(ir, MTK_IRINT_EN);  in mtk_ir_probe()
394 	ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);  in mtk_ir_probe()
403 	val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &  in mtk_ir_probe()
404 	       ir->data->fields[MTK_CHK_PERIOD].mask;  in mtk_ir_probe()
405 	mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,  in mtk_ir_probe()
406 		     ir->data->fields[MTK_CHK_PERIOD].reg);  in mtk_ir_probe()
410 	 * indicating end of IR receiving completion  in mtk_ir_probe()
412 	val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &  in mtk_ir_probe()
413 	       ir->data->fields[MTK_HW_PERIOD].mask;  in mtk_ir_probe()
414 	mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,  in mtk_ir_probe()
415 		     ir->data->fields[MTK_HW_PERIOD].reg);  in mtk_ir_probe()
418 	mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);  in mtk_ir_probe()
420 	/* Enable IR and PWM */  in mtk_ir_probe()
421 	val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);  in mtk_ir_probe()
422 	val |= MTK_OK_COUNT(ir->data->ok_count) |  MTK_PWM_EN | MTK_IR_EN;  in mtk_ir_probe()
423 	mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);  in mtk_ir_probe()
425 	mtk_irq_enable(ir, MTK_IRINT_EN);  in mtk_ir_probe()
427 	dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",  in mtk_ir_probe()
433 	clk_disable_unprepare(ir->bus);  in mtk_ir_probe()
435 	clk_disable_unprepare(ir->clk);  in mtk_ir_probe()
442 	struct mtk_ir *ir = platform_get_drvdata(pdev);  in mtk_ir_remove()  local
446 	 * IRQ handler so that disabling IR interrupt and  in mtk_ir_remove()
449 	mtk_irq_disable(ir, MTK_IRINT_EN);  in mtk_ir_remove()
450 	synchronize_irq(ir->irq);  in mtk_ir_remove()
452 	clk_disable_unprepare(ir->bus);  in mtk_ir_remove()
453 	clk_disable_unprepare(ir->clk);  in mtk_ir_remove()
469 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");