Lines Matching +full:smmu +full:- +full:v2
54 { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
57 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
60 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
63 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
66 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
69 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
81 spin_lock_irqsave(&mc->lock, flags); in terga_mc_block_dma_common()
83 value = mc_readl(mc, rst->control) | BIT(rst->bit); in terga_mc_block_dma_common()
84 mc_writel(mc, value, rst->control); in terga_mc_block_dma_common()
86 spin_unlock_irqrestore(&mc->lock, flags); in terga_mc_block_dma_common()
94 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; in terga_mc_dma_idling_common()
103 spin_lock_irqsave(&mc->lock, flags); in terga_mc_unblock_dma_common()
105 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); in terga_mc_unblock_dma_common()
106 mc_writel(mc, value, rst->control); in terga_mc_unblock_dma_common()
108 spin_unlock_irqrestore(&mc->lock, flags); in terga_mc_unblock_dma_common()
116 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; in terga_mc_reset_status_common()
136 for (i = 0; i < mc->soc->num_resets; i++) in tegra_mc_reset_find()
137 if (mc->soc->resets[i].id == id) in tegra_mc_reset_find()
138 return &mc->soc->resets[i]; in tegra_mc_reset_find()
154 return -ENODEV; in tegra_mc_hotreset_assert()
156 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_assert()
158 return -ENODEV; in tegra_mc_hotreset_assert()
160 if (rst_ops->block_dma) { in tegra_mc_hotreset_assert()
162 err = rst_ops->block_dma(mc, rst); in tegra_mc_hotreset_assert()
164 dev_err(mc->dev, "Failed to block %s DMA: %d\n", in tegra_mc_hotreset_assert()
165 rst->name, err); in tegra_mc_hotreset_assert()
170 if (rst_ops->dma_idling) { in tegra_mc_hotreset_assert()
172 while (!rst_ops->dma_idling(mc, rst)) { in tegra_mc_hotreset_assert()
173 if (!retries--) { in tegra_mc_hotreset_assert()
174 dev_err(mc->dev, "Failed to flush %s DMA\n", in tegra_mc_hotreset_assert()
175 rst->name); in tegra_mc_hotreset_assert()
176 return -EBUSY; in tegra_mc_hotreset_assert()
183 if (rst_ops->hotreset_assert) { in tegra_mc_hotreset_assert()
185 err = rst_ops->hotreset_assert(mc, rst); in tegra_mc_hotreset_assert()
187 dev_err(mc->dev, "Failed to hot reset %s: %d\n", in tegra_mc_hotreset_assert()
188 rst->name, err); in tegra_mc_hotreset_assert()
206 return -ENODEV; in tegra_mc_hotreset_deassert()
208 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_deassert()
210 return -ENODEV; in tegra_mc_hotreset_deassert()
212 if (rst_ops->hotreset_deassert) { in tegra_mc_hotreset_deassert()
214 err = rst_ops->hotreset_deassert(mc, rst); in tegra_mc_hotreset_deassert()
216 dev_err(mc->dev, "Failed to deassert hot reset %s: %d\n", in tegra_mc_hotreset_deassert()
217 rst->name, err); in tegra_mc_hotreset_deassert()
222 if (rst_ops->unblock_dma) { in tegra_mc_hotreset_deassert()
224 err = rst_ops->unblock_dma(mc, rst); in tegra_mc_hotreset_deassert()
226 dev_err(mc->dev, "Failed to unblock %s DMA : %d\n", in tegra_mc_hotreset_deassert()
227 rst->name, err); in tegra_mc_hotreset_deassert()
244 return -ENODEV; in tegra_mc_hotreset_status()
246 rst_ops = mc->soc->reset_ops; in tegra_mc_hotreset_status()
248 return -ENODEV; in tegra_mc_hotreset_status()
250 return rst_ops->reset_status(mc, rst); in tegra_mc_hotreset_status()
263 mc->reset.ops = &tegra_mc_reset_ops; in tegra_mc_reset_setup()
264 mc->reset.owner = THIS_MODULE; in tegra_mc_reset_setup()
265 mc->reset.of_node = mc->dev->of_node; in tegra_mc_reset_setup()
266 mc->reset.of_reset_n_cells = 1; in tegra_mc_reset_setup()
267 mc->reset.nr_resets = mc->soc->num_resets; in tegra_mc_reset_setup()
269 err = reset_controller_register(&mc->reset); in tegra_mc_reset_setup()
283 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); in tegra_mc_setup_latency_allowance()
286 value = readl(mc->regs + MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
289 writel(value, mc->regs + MC_EMEM_ARB_CFG); in tegra_mc_setup_latency_allowance()
292 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_setup_latency_allowance()
293 const struct tegra_mc_la *la = &mc->soc->clients[i].la; in tegra_mc_setup_latency_allowance()
296 value = readl(mc->regs + la->reg); in tegra_mc_setup_latency_allowance()
297 value &= ~(la->mask << la->shift); in tegra_mc_setup_latency_allowance()
298 value |= (la->def & la->mask) << la->shift; in tegra_mc_setup_latency_allowance()
299 writel(value, mc->regs + la->reg); in tegra_mc_setup_latency_allowance()
310 for (i = 0; i < mc->num_timings; i++) { in tegra_mc_write_emem_configuration()
311 if (mc->timings[i].rate == rate) { in tegra_mc_write_emem_configuration()
312 timing = &mc->timings[i]; in tegra_mc_write_emem_configuration()
318 dev_err(mc->dev, "no memory timing registered for rate %lu\n", in tegra_mc_write_emem_configuration()
323 for (i = 0; i < mc->soc->num_emem_regs; ++i) in tegra_mc_write_emem_configuration()
324 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); in tegra_mc_write_emem_configuration()
345 err = of_property_read_u32(node, "clock-frequency", &tmp); in load_one_timing()
347 dev_err(mc->dev, in load_one_timing()
348 "timing %s: failed to read rate\n", node->name); in load_one_timing()
352 timing->rate = tmp; in load_one_timing()
353 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, in load_one_timing()
355 if (!timing->emem_data) in load_one_timing()
356 return -ENOMEM; in load_one_timing()
358 err = of_property_read_u32_array(node, "nvidia,emem-configuration", in load_one_timing()
359 timing->emem_data, in load_one_timing()
360 mc->soc->num_emem_regs); in load_one_timing()
362 dev_err(mc->dev, in load_one_timing()
364 node->name); in load_one_timing()
378 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), in load_timings()
380 if (!mc->timings) in load_timings()
381 return -ENOMEM; in load_timings()
383 mc->num_timings = child_count; in load_timings()
386 timing = &mc->timings[i++]; in load_timings()
406 mc->num_timings = 0; in tegra_mc_setup_timings()
408 for_each_child_of_node(mc->dev->of_node, node) { in tegra_mc_setup_timings()
409 err = of_property_read_u32(node, "nvidia,ram-code", in tegra_mc_setup_timings()
421 if (mc->num_timings == 0) in tegra_mc_setup_timings()
422 dev_warn(mc->dev, in tegra_mc_setup_timings()
446 [6] = "SMMU translation error",
456 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra_mc_irq()
473 if (mc->soc->num_address_bits > 32) { in tegra_mc_irq()
490 id = value & mc->soc->client_id_mask; in tegra_mc_irq()
492 for (i = 0; i < mc->soc->num_clients; i++) { in tegra_mc_irq()
493 if (mc->soc->clients[i].id == id) { in tegra_mc_irq()
494 client = mc->soc->clients[i].name; in tegra_mc_irq()
511 perm[2] = '-'; in tegra_mc_irq()
516 perm[3] = '-'; in tegra_mc_irq()
519 perm[4] = '-'; in tegra_mc_irq()
535 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", in tegra_mc_irq()
553 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; in tegra20_mc_irq()
570 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
578 dev_err_ratelimited(mc->dev, "%s\n", error); in tegra20_mc_irq()
585 id = value & mc->soc->client_id_mask; in tegra20_mc_irq()
598 client = mc->soc->clients[id].name; in tegra20_mc_irq()
601 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", in tegra20_mc_irq()
620 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); in tegra_mc_probe()
622 return -ENODEV; in tegra_mc_probe()
624 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); in tegra_mc_probe()
626 return -ENOMEM; in tegra_mc_probe()
629 spin_lock_init(&mc->lock); in tegra_mc_probe()
630 mc->soc = match->data; in tegra_mc_probe()
631 mc->dev = &pdev->dev; in tegra_mc_probe()
634 mc->tick = 30; in tegra_mc_probe()
637 mc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_mc_probe()
638 if (IS_ERR(mc->regs)) in tegra_mc_probe()
639 return PTR_ERR(mc->regs); in tegra_mc_probe()
642 if (mc->soc == &tegra20_mc_soc) { in tegra_mc_probe()
644 mc->regs2 = devm_ioremap_resource(&pdev->dev, res); in tegra_mc_probe()
645 if (IS_ERR(mc->regs2)) in tegra_mc_probe()
646 return PTR_ERR(mc->regs2); in tegra_mc_probe()
652 mc->clk = devm_clk_get(&pdev->dev, "mc"); in tegra_mc_probe()
653 if (IS_ERR(mc->clk)) { in tegra_mc_probe()
654 dev_err(&pdev->dev, "failed to get MC clock: %ld\n", in tegra_mc_probe()
655 PTR_ERR(mc->clk)); in tegra_mc_probe()
656 return PTR_ERR(mc->clk); in tegra_mc_probe()
661 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", in tegra_mc_probe()
670 dev_err(&pdev->dev, "failed to setup timings: %d\n", in tegra_mc_probe()
676 mc->irq = platform_get_irq(pdev, 0); in tegra_mc_probe()
677 if (mc->irq < 0) { in tegra_mc_probe()
678 dev_err(&pdev->dev, "interrupt not specified\n"); in tegra_mc_probe()
679 return mc->irq; in tegra_mc_probe()
682 WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n"); in tegra_mc_probe()
684 mc_writel(mc, mc->soc->intmask, MC_INTMASK); in tegra_mc_probe()
686 err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED, in tegra_mc_probe()
687 dev_name(&pdev->dev), mc); in tegra_mc_probe()
689 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, in tegra_mc_probe()
696 dev_err(&pdev->dev, "failed to register reset controller: %d\n", in tegra_mc_probe()
700 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); in tegra_mc_probe()
701 if (IS_ERR(mc->smmu)) in tegra_mc_probe()
702 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", in tegra_mc_probe()
703 PTR_ERR(mc->smmu)); in tegra_mc_probe()
711 .name = "tegra-mc",
727 MODULE_LICENSE("GPL v2");