Lines Matching +full:0 +full:x228
18 .id = 0x00,
22 .id = 0x01,
26 .reg = 0x228,
30 .reg = 0x2e8,
31 .shift = 0,
32 .mask = 0xff,
33 .def = 0x4e,
36 .id = 0x02,
40 .reg = 0x228,
44 .reg = 0x2f4,
45 .shift = 0,
46 .mask = 0xff,
47 .def = 0x4e,
50 .id = 0x03,
54 .reg = 0x228,
58 .reg = 0x2e8,
60 .mask = 0xff,
61 .def = 0x4e,
64 .id = 0x04,
68 .reg = 0x228,
72 .reg = 0x2f4,
74 .mask = 0xff,
75 .def = 0x4e,
78 .id = 0x05,
82 .reg = 0x228,
86 .reg = 0x2ec,
87 .shift = 0,
88 .mask = 0xff,
89 .def = 0x4e,
92 .id = 0x06,
96 .reg = 0x228,
100 .reg = 0x2f8,
101 .shift = 0,
102 .mask = 0xff,
103 .def = 0x4e,
106 .id = 0x09,
110 .reg = 0x228,
114 .reg = 0x300,
115 .shift = 0,
116 .mask = 0xff,
117 .def = 0x33,
120 .id = 0x0a,
124 .reg = 0x228,
128 .reg = 0x308,
129 .shift = 0,
130 .mask = 0xff,
131 .def = 0x09,
134 .id = 0x0b,
138 .reg = 0x228,
142 .reg = 0x308,
144 .mask = 0xff,
145 .def = 0x09,
148 .id = 0x0f,
152 .reg = 0x228,
156 .reg = 0x2e4,
157 .shift = 0,
158 .mask = 0xff,
159 .def = 0x04,
162 .id = 0x10,
166 .reg = 0x228,
170 .reg = 0x2f0,
171 .shift = 0,
172 .mask = 0xff,
173 .def = 0x68,
176 .id = 0x11,
180 .reg = 0x228,
184 .reg = 0x2fc,
185 .shift = 0,
186 .mask = 0xff,
187 .def = 0x68,
190 .id = 0x12,
194 .reg = 0x228,
198 .reg = 0x334,
199 .shift = 0,
200 .mask = 0xff,
201 .def = 0x0c,
204 .id = 0x13,
208 .reg = 0x228,
212 .reg = 0x33c,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x0c,
218 .id = 0x14,
222 .reg = 0x228,
226 .reg = 0x30c,
227 .shift = 0,
228 .mask = 0xff,
229 .def = 0x0a,
232 .id = 0x15,
236 .reg = 0x228,
240 .reg = 0x318,
241 .shift = 0,
242 .mask = 0xff,
243 .def = 0xff,
246 .id = 0x16,
250 .reg = 0x228,
254 .reg = 0x310,
255 .shift = 0,
256 .mask = 0xff,
257 .def = 0x10,
260 .id = 0x17,
264 .reg = 0x228,
268 .reg = 0x310,
270 .mask = 0xff,
271 .def = 0xa5,
274 .id = 0x18,
278 .reg = 0x228,
282 .reg = 0x334,
284 .mask = 0xff,
285 .def = 0x0b,
288 .id = 0x1c,
292 .reg = 0x228,
296 .reg = 0x328,
297 .shift = 0,
298 .mask = 0xff,
299 .def = 0x80,
302 .id = 0x1d,
306 .reg = 0x228,
310 .reg = 0x344,
311 .shift = 0,
312 .mask = 0xff,
313 .def = 0x50,
316 .id = 0x1e,
320 .reg = 0x228,
324 .reg = 0x344,
326 .mask = 0xff,
327 .def = 0xe8,
330 .id = 0x20,
334 .reg = 0x22c,
335 .bit = 0,
338 .reg = 0x338,
339 .shift = 0,
340 .mask = 0xff,
341 .def = 0x0c,
344 .id = 0x22,
348 .reg = 0x22c,
352 .reg = 0x354,
353 .shift = 0,
354 .mask = 0xff,
355 .def = 0xff,
358 .id = 0x23,
362 .reg = 0x22c,
366 .reg = 0x354,
368 .mask = 0xff,
369 .def = 0xff,
372 .id = 0x24,
376 .reg = 0x22c,
380 .reg = 0x358,
381 .shift = 0,
382 .mask = 0xff,
383 .def = 0xb8,
386 .id = 0x25,
390 .reg = 0x22c,
394 .reg = 0x358,
396 .mask = 0xff,
397 .def = 0xee,
400 .id = 0x26,
404 .reg = 0x324,
405 .shift = 0,
406 .mask = 0xff,
407 .def = 0x04,
410 .id = 0x27,
414 .reg = 0x320,
415 .shift = 0,
416 .mask = 0xff,
417 .def = 0x04,
420 .id = 0x28,
424 .reg = 0x22c,
428 .reg = 0x300,
430 .mask = 0xff,
431 .def = 0x33,
434 .id = 0x29,
438 .reg = 0x22c,
442 .reg = 0x304,
443 .shift = 0,
444 .mask = 0xff,
445 .def = 0x6c,
448 .id = 0x2a,
452 .reg = 0x22c,
456 .reg = 0x304,
458 .mask = 0xff,
459 .def = 0x6c,
462 .id = 0x2b,
466 .reg = 0x22c,
470 .reg = 0x328,
472 .mask = 0xff,
473 .def = 0x80,
476 .id = 0x2c,
480 .reg = 0x22c,
484 .reg = 0x364,
485 .shift = 0,
486 .mask = 0xff,
487 .def = 0x47,
490 .id = 0x2d,
494 .reg = 0x22c,
498 .reg = 0x368,
499 .shift = 0,
500 .mask = 0xff,
501 .def = 0xff,
504 .id = 0x2e,
508 .reg = 0x22c,
512 .reg = 0x368,
514 .mask = 0xff,
515 .def = 0xff,
518 .id = 0x2f,
522 .reg = 0x22c,
526 .reg = 0x36c,
527 .shift = 0,
528 .mask = 0xff,
529 .def = 0x47,
532 .id = 0x30,
536 .reg = 0x22c,
540 .reg = 0x30c,
542 .mask = 0xff,
543 .def = 0x9,
546 .id = 0x32,
550 .reg = 0x22c,
554 .reg = 0x2e4,
556 .mask = 0xff,
557 .def = 0x0e,
560 .id = 0x33,
564 .reg = 0x22c,
568 .reg = 0x338,
570 .mask = 0xff,
571 .def = 0x10,
574 .id = 0x34,
578 .reg = 0x22c,
582 .reg = 0x340,
583 .shift = 0,
584 .mask = 0xff,
585 .def = 0x10,
588 .id = 0x35,
592 .reg = 0x22c,
596 .reg = 0x318,
598 .mask = 0xff,
599 .def = 0xff,
602 .id = 0x36,
606 .reg = 0x22c,
610 .reg = 0x314,
611 .shift = 0,
612 .mask = 0xff,
613 .def = 0x25,
616 .id = 0x37,
620 .reg = 0x22c,
624 .reg = 0x31c,
625 .shift = 0,
626 .mask = 0xff,
627 .def = 0xff,
630 .id = 0x38,
634 .reg = 0x324,
636 .mask = 0xff,
637 .def = 0x80,
640 .id = 0x39,
644 .reg = 0x320,
646 .mask = 0xff,
647 .def = 0x0e,
650 .id = 0x3b,
654 .reg = 0x22c,
658 .reg = 0x348,
659 .shift = 0,
660 .mask = 0xff,
661 .def = 0xa5,
664 .id = 0x3c,
668 .reg = 0x22c,
672 .reg = 0x348,
674 .mask = 0xff,
675 .def = 0xe8,
678 .id = 0x3e,
682 .reg = 0x22c,
686 .reg = 0x35c,
687 .shift = 0,
688 .mask = 0xff,
689 .def = 0xff,
692 .id = 0x3f,
696 .reg = 0x22c,
700 .reg = 0x35c,
702 .mask = 0xff,
703 .def = 0xff,
706 .id = 0x40,
710 .reg = 0x230,
711 .bit = 0,
714 .reg = 0x360,
715 .shift = 0,
716 .mask = 0xff,
717 .def = 0x89,
720 .id = 0x41,
724 .reg = 0x230,
728 .reg = 0x360,
730 .mask = 0xff,
731 .def = 0x59,
734 .id = 0x4a,
738 .reg = 0x230,
742 .reg = 0x37c,
743 .shift = 0,
744 .mask = 0xff,
745 .def = 0xa5,
748 .id = 0x4b,
752 .reg = 0x230,
756 .reg = 0x37c,
758 .mask = 0xff,
759 .def = 0xa5,
762 .id = 0x4c,
766 .reg = 0x230,
770 .reg = 0x380,
771 .shift = 0,
772 .mask = 0xff,
773 .def = 0xa5,
776 .id = 0x4d,
780 .reg = 0x230,
784 .reg = 0x380,
786 .mask = 0xff,
787 .def = 0xa5,
790 .id = 0x4e,
794 .reg = 0x230,
798 .reg = 0x388,
799 .shift = 0,
800 .mask = 0xff,
801 .def = 0x10,
804 .id = 0x4f,
808 .reg = 0x230,
812 .reg = 0x384,
813 .shift = 0,
814 .mask = 0xff,
815 .def = 0x0c,
818 .id = 0x50,
822 .reg = 0x230,
826 .reg = 0x388,
828 .mask = 0xff,
829 .def = 0x10,
832 .id = 0x51,
836 .reg = 0x230,
840 .reg = 0x384,
842 .mask = 0xff,
843 .def = 0x0c,
846 .id = 0x52,
850 .reg = 0x38c,
851 .shift = 0,
852 .mask = 0xff,
853 .def = 0x04,
856 .id = 0x53,
860 .reg = 0x38c,
862 .mask = 0xff,
863 .def = 0x0e,
866 .id = 0x54,
870 .reg = 0x230,
874 .reg = 0x390,
875 .shift = 0,
876 .mask = 0xff,
877 .def = 0x50,
880 .id = 0x55,
884 .reg = 0x230,
888 .reg = 0x390,
890 .mask = 0xff,
891 .def = 0x50,
897 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
898 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
899 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
900 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
901 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
902 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
903 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
904 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
905 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
906 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
907 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
908 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
909 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
910 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
911 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
912 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
951 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
952 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
953 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
954 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
955 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
956 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
957 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
958 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
959 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
960 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
961 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
962 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
963 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
964 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
965 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
966 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
974 .client_id_mask = 0x7f,