Lines Matching +full:reg +full:- +full:shift
12 #include <dt-bindings/memory/tegra114-mc.h>
26 .reg = 0x228,
30 .reg = 0x2e8,
31 .shift = 0,
40 .reg = 0x228,
44 .reg = 0x2f4,
45 .shift = 0,
54 .reg = 0x228,
58 .reg = 0x2e8,
59 .shift = 16,
68 .reg = 0x228,
72 .reg = 0x2f4,
73 .shift = 16,
82 .reg = 0x228,
86 .reg = 0x2ec,
87 .shift = 0,
96 .reg = 0x228,
100 .reg = 0x2f8,
101 .shift = 0,
110 .reg = 0x228,
114 .reg = 0x300,
115 .shift = 0,
124 .reg = 0x228,
128 .reg = 0x308,
129 .shift = 0,
138 .reg = 0x228,
142 .reg = 0x308,
143 .shift = 16,
152 .reg = 0x228,
156 .reg = 0x2e4,
157 .shift = 0,
166 .reg = 0x228,
170 .reg = 0x2f0,
171 .shift = 0,
180 .reg = 0x228,
184 .reg = 0x2fc,
185 .shift = 0,
194 .reg = 0x228,
198 .reg = 0x334,
199 .shift = 0,
208 .reg = 0x228,
212 .reg = 0x33c,
213 .shift = 0,
222 .reg = 0x228,
226 .reg = 0x30c,
227 .shift = 0,
236 .reg = 0x228,
240 .reg = 0x318,
241 .shift = 0,
250 .reg = 0x228,
254 .reg = 0x310,
255 .shift = 0,
264 .reg = 0x228,
268 .reg = 0x310,
269 .shift = 16,
278 .reg = 0x228,
282 .reg = 0x334,
283 .shift = 16,
292 .reg = 0x228,
296 .reg = 0x328,
297 .shift = 0,
306 .reg = 0x228,
310 .reg = 0x344,
311 .shift = 0,
320 .reg = 0x228,
324 .reg = 0x344,
325 .shift = 16,
334 .reg = 0x22c,
338 .reg = 0x338,
339 .shift = 0,
348 .reg = 0x22c,
352 .reg = 0x354,
353 .shift = 0,
362 .reg = 0x22c,
366 .reg = 0x354,
367 .shift = 16,
376 .reg = 0x22c,
380 .reg = 0x358,
381 .shift = 0,
390 .reg = 0x22c,
394 .reg = 0x358,
395 .shift = 16,
404 .reg = 0x324,
405 .shift = 0,
414 .reg = 0x320,
415 .shift = 0,
424 .reg = 0x22c,
428 .reg = 0x300,
429 .shift = 16,
438 .reg = 0x22c,
442 .reg = 0x304,
443 .shift = 0,
452 .reg = 0x22c,
456 .reg = 0x304,
457 .shift = 16,
466 .reg = 0x22c,
470 .reg = 0x328,
471 .shift = 16,
480 .reg = 0x22c,
484 .reg = 0x364,
485 .shift = 0,
494 .reg = 0x22c,
498 .reg = 0x368,
499 .shift = 0,
508 .reg = 0x22c,
512 .reg = 0x368,
513 .shift = 16,
522 .reg = 0x22c,
526 .reg = 0x36c,
527 .shift = 0,
536 .reg = 0x22c,
540 .reg = 0x30c,
541 .shift = 16,
550 .reg = 0x22c,
554 .reg = 0x2e4,
555 .shift = 16,
564 .reg = 0x22c,
568 .reg = 0x338,
569 .shift = 16,
578 .reg = 0x22c,
582 .reg = 0x340,
583 .shift = 0,
592 .reg = 0x22c,
596 .reg = 0x318,
597 .shift = 16,
606 .reg = 0x22c,
610 .reg = 0x314,
611 .shift = 0,
620 .reg = 0x22c,
624 .reg = 0x31c,
625 .shift = 0,
634 .reg = 0x324,
635 .shift = 16,
644 .reg = 0x320,
645 .shift = 16,
654 .reg = 0x22c,
658 .reg = 0x348,
659 .shift = 0,
668 .reg = 0x22c,
672 .reg = 0x348,
673 .shift = 16,
682 .reg = 0x22c,
686 .reg = 0x35c,
687 .shift = 0,
696 .reg = 0x22c,
700 .reg = 0x35c,
701 .shift = 16,
710 .reg = 0x230,
714 .reg = 0x360,
715 .shift = 0,
724 .reg = 0x230,
728 .reg = 0x360,
729 .shift = 16,
738 .reg = 0x230,
742 .reg = 0x37c,
743 .shift = 0,
752 .reg = 0x230,
756 .reg = 0x37c,
757 .shift = 16,
766 .reg = 0x230,
770 .reg = 0x380,
771 .shift = 0,
780 .reg = 0x230,
784 .reg = 0x380,
785 .shift = 16,
794 .reg = 0x230,
798 .reg = 0x388,
799 .shift = 0,
808 .reg = 0x230,
812 .reg = 0x384,
813 .shift = 0,
822 .reg = 0x230,
826 .reg = 0x388,
827 .shift = 16,
836 .reg = 0x230,
840 .reg = 0x384,
841 .shift = 16,
850 .reg = 0x38c,
851 .shift = 0,
860 .reg = 0x38c,
861 .shift = 16,
870 .reg = 0x230,
874 .reg = 0x390,
875 .shift = 0,
884 .reg = 0x230,
888 .reg = 0x390,
889 .shift = 16,
897 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
898 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
899 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
900 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
901 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
902 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
903 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
904 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
905 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
906 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
907 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
908 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
909 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
910 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
911 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
912 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },