Lines Matching +full:0 +full:x234
16 #define MC_EMEM_ARB_CFG 0x90
17 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
18 #define MC_EMEM_ARB_TIMING_RCD 0x98
19 #define MC_EMEM_ARB_TIMING_RP 0x9c
20 #define MC_EMEM_ARB_TIMING_RC 0xa0
21 #define MC_EMEM_ARB_TIMING_RAS 0xa4
22 #define MC_EMEM_ARB_TIMING_FAW 0xa8
23 #define MC_EMEM_ARB_TIMING_RRD 0xac
24 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
25 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
26 #define MC_EMEM_ARB_TIMING_R2R 0xb8
27 #define MC_EMEM_ARB_TIMING_W2W 0xbc
28 #define MC_EMEM_ARB_TIMING_R2W 0xc0
29 #define MC_EMEM_ARB_TIMING_W2R 0xc4
30 #define MC_EMEM_ARB_DA_TURNS 0xd0
31 #define MC_EMEM_ARB_DA_COVERS 0xd4
32 #define MC_EMEM_ARB_MISC0 0xd8
33 #define MC_EMEM_ARB_MISC1 0xdc
34 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
60 .id = 0x00,
64 .id = 0x01,
68 .reg = 0x228,
72 .reg = 0x2e8,
73 .shift = 0,
74 .mask = 0xff,
75 .def = 0xc2,
78 .id = 0x02,
82 .reg = 0x228,
86 .reg = 0x2f4,
87 .shift = 0,
88 .mask = 0xff,
89 .def = 0xc6,
92 .id = 0x03,
96 .reg = 0x228,
100 .reg = 0x2e8,
102 .mask = 0xff,
103 .def = 0x50,
106 .id = 0x04,
110 .reg = 0x228,
114 .reg = 0x2f4,
116 .mask = 0xff,
117 .def = 0x50,
120 .id = 0x05,
124 .reg = 0x228,
128 .reg = 0x2ec,
129 .shift = 0,
130 .mask = 0xff,
131 .def = 0x50,
134 .id = 0x06,
138 .reg = 0x228,
142 .reg = 0x2f8,
143 .shift = 0,
144 .mask = 0xff,
145 .def = 0x50,
148 .id = 0x0e,
152 .reg = 0x228,
156 .reg = 0x2e0,
157 .shift = 0,
158 .mask = 0xff,
159 .def = 0x13,
162 .id = 0x0f,
166 .reg = 0x228,
170 .reg = 0x2e4,
171 .shift = 0,
172 .mask = 0xff,
173 .def = 0x04,
176 .id = 0x10,
180 .reg = 0x228,
184 .reg = 0x2f0,
185 .shift = 0,
186 .mask = 0xff,
187 .def = 0x50,
190 .id = 0x11,
194 .reg = 0x228,
198 .reg = 0x2fc,
199 .shift = 0,
200 .mask = 0xff,
201 .def = 0x50,
204 .id = 0x15,
208 .reg = 0x228,
212 .reg = 0x318,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x24,
218 .id = 0x16,
222 .reg = 0x228,
226 .reg = 0x310,
227 .shift = 0,
228 .mask = 0xff,
229 .def = 0x1e,
232 .id = 0x17,
236 .reg = 0x228,
240 .reg = 0x310,
242 .mask = 0xff,
243 .def = 0x50,
246 .id = 0x1c,
250 .reg = 0x228,
254 .reg = 0x328,
255 .shift = 0,
256 .mask = 0xff,
257 .def = 0x23,
260 .id = 0x1d,
264 .reg = 0x228,
268 .reg = 0x344,
269 .shift = 0,
270 .mask = 0xff,
271 .def = 0x49,
274 .id = 0x1e,
278 .reg = 0x228,
282 .reg = 0x344,
284 .mask = 0xff,
285 .def = 0x1a,
288 .id = 0x1f,
292 .reg = 0x228,
296 .reg = 0x350,
297 .shift = 0,
298 .mask = 0xff,
299 .def = 0x65,
302 .id = 0x22,
306 .reg = 0x22c,
310 .reg = 0x354,
311 .shift = 0,
312 .mask = 0xff,
313 .def = 0x4f,
316 .id = 0x23,
320 .reg = 0x22c,
324 .reg = 0x354,
326 .mask = 0xff,
327 .def = 0x3d,
330 .id = 0x24,
334 .reg = 0x22c,
338 .reg = 0x358,
339 .shift = 0,
340 .mask = 0xff,
341 .def = 0x66,
344 .id = 0x25,
348 .reg = 0x22c,
352 .reg = 0x358,
354 .mask = 0xff,
355 .def = 0xa5,
358 .id = 0x26,
362 .reg = 0x324,
363 .shift = 0,
364 .mask = 0xff,
365 .def = 0x04,
368 .id = 0x27,
372 .reg = 0x320,
373 .shift = 0,
374 .mask = 0xff,
375 .def = 0x04,
378 .id = 0x2b,
382 .reg = 0x22c,
386 .reg = 0x328,
388 .mask = 0xff,
389 .def = 0x80,
392 .id = 0x31,
396 .reg = 0x22c,
400 .reg = 0x2e0,
402 .mask = 0xff,
403 .def = 0x80,
406 .id = 0x32,
410 .reg = 0x22c,
414 .reg = 0x2e4,
416 .mask = 0xff,
417 .def = 0x80,
420 .id = 0x35,
424 .reg = 0x22c,
428 .reg = 0x318,
430 .mask = 0xff,
431 .def = 0x80,
434 .id = 0x36,
438 .reg = 0x22c,
442 .reg = 0x314,
443 .shift = 0,
444 .mask = 0xff,
445 .def = 0x80,
448 .id = 0x38,
452 .reg = 0x324,
454 .mask = 0xff,
455 .def = 0x80,
458 .id = 0x39,
462 .reg = 0x320,
464 .mask = 0xff,
465 .def = 0x80,
468 .id = 0x3b,
472 .reg = 0x22c,
476 .reg = 0x348,
477 .shift = 0,
478 .mask = 0xff,
479 .def = 0x80,
482 .id = 0x3c,
486 .reg = 0x22c,
490 .reg = 0x348,
492 .mask = 0xff,
493 .def = 0x80,
496 .id = 0x3d,
500 .reg = 0x22c,
504 .reg = 0x350,
506 .mask = 0xff,
507 .def = 0x65,
510 .id = 0x3e,
514 .reg = 0x22c,
518 .reg = 0x35c,
519 .shift = 0,
520 .mask = 0xff,
521 .def = 0x80,
524 .id = 0x3f,
528 .reg = 0x22c,
532 .reg = 0x35c,
534 .mask = 0xff,
535 .def = 0x80,
538 .id = 0x40,
542 .reg = 0x230,
543 .bit = 0,
546 .reg = 0x360,
547 .shift = 0,
548 .mask = 0xff,
549 .def = 0x80,
552 .id = 0x41,
556 .reg = 0x230,
560 .reg = 0x360,
562 .mask = 0xff,
563 .def = 0x80,
566 .id = 0x44,
570 .reg = 0x230,
574 .reg = 0x370,
575 .shift = 0,
576 .mask = 0xff,
577 .def = 0x18,
580 .id = 0x46,
584 .reg = 0x230,
588 .reg = 0x374,
589 .shift = 0,
590 .mask = 0xff,
591 .def = 0x80,
594 .id = 0x47,
598 .reg = 0x230,
602 .reg = 0x374,
604 .mask = 0xff,
605 .def = 0x80,
608 .id = 0x4a,
612 .reg = 0x230,
616 .reg = 0x37c,
617 .shift = 0,
618 .mask = 0xff,
619 .def = 0x39,
622 .id = 0x4b,
626 .reg = 0x230,
630 .reg = 0x37c,
632 .mask = 0xff,
633 .def = 0x80,
636 .id = 0x4c,
640 .reg = 0x230,
644 .reg = 0x380,
645 .shift = 0,
646 .mask = 0xff,
647 .def = 0x39,
650 .id = 0x4d,
654 .reg = 0x230,
658 .reg = 0x380,
660 .mask = 0xff,
661 .def = 0x80,
664 .id = 0x4e,
668 .reg = 0x230,
672 .reg = 0x384,
673 .shift = 0,
674 .mask = 0xff,
675 .def = 0x18,
678 .id = 0x50,
682 .reg = 0x230,
686 .reg = 0x388,
687 .shift = 0,
688 .mask = 0xff,
689 .def = 0x80,
692 .id = 0x51,
696 .reg = 0x230,
700 .reg = 0x388,
702 .mask = 0xff,
703 .def = 0x80,
706 .id = 0x54,
710 .reg = 0x230,
714 .reg = 0x390,
715 .shift = 0,
716 .mask = 0xff,
717 .def = 0x9b,
720 .id = 0x55,
724 .reg = 0x230,
728 .reg = 0x390,
730 .mask = 0xff,
731 .def = 0x80,
734 .id = 0x56,
738 .reg = 0x230,
742 .reg = 0x3a4,
743 .shift = 0,
744 .mask = 0xff,
745 .def = 0x04,
748 .id = 0x57,
752 .reg = 0x230,
756 .reg = 0x3a4,
758 .mask = 0xff,
759 .def = 0x80,
762 .id = 0x58,
767 .reg = 0x230,
771 .reg = 0x3c8,
772 .shift = 0,
773 .mask = 0xff,
774 .def = 0x1a,
777 .id = 0x59,
782 .reg = 0x230,
786 .reg = 0x3c8,
788 .mask = 0xff,
789 .def = 0x80,
792 .id = 0x5a,
796 .reg = 0x230,
800 .reg = 0x2f0,
802 .mask = 0xff,
803 .def = 0x50,
806 .id = 0x60,
810 .reg = 0x234,
811 .bit = 0,
814 .reg = 0x3b8,
815 .shift = 0,
816 .mask = 0xff,
817 .def = 0x49,
820 .id = 0x61,
824 .reg = 0x234,
828 .reg = 0x3bc,
829 .shift = 0,
830 .mask = 0xff,
831 .def = 0x49,
834 .id = 0x62,
838 .reg = 0x234,
842 .reg = 0x3c0,
843 .shift = 0,
844 .mask = 0xff,
845 .def = 0x49,
848 .id = 0x63,
852 .reg = 0x234,
856 .reg = 0x3c4,
857 .shift = 0,
858 .mask = 0xff,
859 .def = 0x49,
862 .id = 0x64,
866 .reg = 0x234,
870 .reg = 0x3b8,
872 .mask = 0xff,
873 .def = 0x80,
876 .id = 0x65,
880 .reg = 0x234,
884 .reg = 0x3bc,
886 .mask = 0xff,
887 .def = 0x80,
890 .id = 0x66,
894 .reg = 0x234,
898 .reg = 0x3c0,
900 .mask = 0xff,
901 .def = 0x80,
904 .id = 0x67,
908 .reg = 0x234,
912 .reg = 0x3c4,
914 .mask = 0xff,
915 .def = 0x80,
918 .id = 0x6c,
922 .reg = 0x234,
926 .reg = 0x394,
927 .shift = 0,
928 .mask = 0xff,
929 .def = 0x1a,
932 .id = 0x6d,
936 .reg = 0x234,
940 .reg = 0x394,
942 .mask = 0xff,
943 .def = 0x80,
946 .id = 0x72,
950 .reg = 0x234,
954 .reg = 0x398,
955 .shift = 0,
956 .mask = 0xff,
957 .def = 0x80,
960 .id = 0x73,
964 .reg = 0x234,
968 .reg = 0x3c8,
969 .shift = 0,
970 .mask = 0xff,
971 .def = 0x50,
977 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
978 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
979 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
980 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
981 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
982 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
983 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
984 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
985 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
986 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
987 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
988 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
989 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
990 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
991 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
992 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
993 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
994 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
995 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
996 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
997 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
998 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
999 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1025 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1026 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1027 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1028 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1029 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1030 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1031 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1032 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1033 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1034 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1035 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1036 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1037 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1038 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1039 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1040 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1041 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1042 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1043 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1044 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1045 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1046 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1047 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1048 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1070 .client_id_mask = 0x7f,
1102 .client_id_mask = 0x7f,