Lines Matching +full:0 +full:x234
15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0xc6,
47 .id = 0x03,
51 .reg = 0x228,
55 .reg = 0x2e8,
57 .mask = 0xff,
58 .def = 0x50,
61 .id = 0x04,
65 .reg = 0x228,
69 .reg = 0x2f4,
71 .mask = 0xff,
72 .def = 0x50,
75 .id = 0x05,
79 .reg = 0x228,
83 .reg = 0x2ec,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0x50,
89 .id = 0x06,
93 .reg = 0x228,
97 .reg = 0x2f8,
98 .shift = 0,
99 .mask = 0xff,
100 .def = 0x50,
103 .id = 0x0e,
107 .reg = 0x228,
111 .reg = 0x2e0,
112 .shift = 0,
113 .mask = 0xff,
114 .def = 0x13,
117 .id = 0x0f,
121 .reg = 0x228,
125 .reg = 0x2e4,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x04,
131 .id = 0x10,
135 .reg = 0x228,
139 .reg = 0x2f0,
140 .shift = 0,
141 .mask = 0xff,
142 .def = 0x50,
145 .id = 0x11,
149 .reg = 0x228,
153 .reg = 0x2fc,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x50,
159 .id = 0x15,
163 .reg = 0x228,
167 .reg = 0x318,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x24,
173 .id = 0x16,
177 .reg = 0x228,
181 .reg = 0x310,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x1e,
187 .id = 0x17,
191 .reg = 0x228,
195 .reg = 0x310,
197 .mask = 0xff,
198 .def = 0x50,
201 .id = 0x1c,
205 .reg = 0x228,
209 .reg = 0x328,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x23,
215 .id = 0x1d,
219 .reg = 0x228,
223 .reg = 0x344,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x49,
229 .id = 0x1e,
233 .reg = 0x228,
237 .reg = 0x344,
239 .mask = 0xff,
240 .def = 0x1a,
243 .id = 0x1f,
247 .reg = 0x228,
251 .reg = 0x350,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x65,
257 .id = 0x27,
261 .reg = 0x320,
262 .shift = 0,
263 .mask = 0xff,
264 .def = 0x04,
267 .id = 0x2b,
271 .reg = 0x22c,
275 .reg = 0x328,
277 .mask = 0xff,
278 .def = 0x80,
281 .id = 0x31,
285 .reg = 0x22c,
289 .reg = 0x2e0,
291 .mask = 0xff,
292 .def = 0x80,
295 .id = 0x32,
299 .reg = 0x22c,
303 .reg = 0x2e4,
305 .mask = 0xff,
306 .def = 0x80,
309 .id = 0x35,
313 .reg = 0x22c,
317 .reg = 0x318,
319 .mask = 0xff,
320 .def = 0x80,
323 .id = 0x36,
327 .reg = 0x22c,
331 .reg = 0x314,
332 .shift = 0,
333 .mask = 0xff,
334 .def = 0x80,
337 .id = 0x39,
341 .reg = 0x320,
343 .mask = 0xff,
344 .def = 0x80,
347 .id = 0x3b,
351 .reg = 0x22c,
355 .reg = 0x348,
356 .shift = 0,
357 .mask = 0xff,
358 .def = 0x80,
361 .id = 0x3c,
365 .reg = 0x22c,
369 .reg = 0x348,
371 .mask = 0xff,
372 .def = 0x80,
375 .id = 0x3d,
379 .reg = 0x22c,
383 .reg = 0x350,
385 .mask = 0xff,
386 .def = 0x65,
389 .id = 0x44,
393 .reg = 0x230,
397 .reg = 0x370,
398 .shift = 0,
399 .mask = 0xff,
400 .def = 0x18,
403 .id = 0x46,
407 .reg = 0x230,
411 .reg = 0x374,
412 .shift = 0,
413 .mask = 0xff,
414 .def = 0x80,
417 .id = 0x47,
421 .reg = 0x230,
425 .reg = 0x374,
427 .mask = 0xff,
428 .def = 0x80,
431 .id = 0x4a,
435 .reg = 0x230,
439 .reg = 0x37c,
440 .shift = 0,
441 .mask = 0xff,
442 .def = 0x39,
445 .id = 0x4b,
449 .reg = 0x230,
453 .reg = 0x37c,
455 .mask = 0xff,
456 .def = 0x80,
459 .id = 0x4c,
463 .reg = 0x230,
467 .reg = 0x380,
468 .shift = 0,
469 .mask = 0xff,
470 .def = 0x39,
473 .id = 0x4d,
477 .reg = 0x230,
481 .reg = 0x380,
483 .mask = 0xff,
484 .def = 0x80,
487 .id = 0x4e,
491 .reg = 0x230,
495 .reg = 0x384,
496 .shift = 0,
497 .mask = 0xff,
498 .def = 0x18,
501 .id = 0x50,
505 .reg = 0x230,
509 .reg = 0x388,
510 .shift = 0,
511 .mask = 0xff,
512 .def = 0x80,
515 .id = 0x51,
519 .reg = 0x230,
523 .reg = 0x388,
525 .mask = 0xff,
526 .def = 0x80,
529 .id = 0x54,
533 .reg = 0x230,
537 .reg = 0x390,
538 .shift = 0,
539 .mask = 0xff,
540 .def = 0x9b,
543 .id = 0x55,
547 .reg = 0x230,
551 .reg = 0x390,
553 .mask = 0xff,
554 .def = 0x80,
557 .id = 0x56,
561 .reg = 0x230,
565 .reg = 0x3a4,
566 .shift = 0,
567 .mask = 0xff,
568 .def = 0x04,
571 .id = 0x57,
575 .reg = 0x230,
579 .reg = 0x3a4,
581 .mask = 0xff,
582 .def = 0x80,
585 .id = 0x58,
590 .reg = 0x230,
594 .reg = 0x3c8,
595 .shift = 0,
596 .mask = 0xff,
597 .def = 0x1a,
600 .id = 0x59,
605 .reg = 0x230,
609 .reg = 0x3c8,
611 .mask = 0xff,
612 .def = 0x80,
615 .id = 0x5a,
619 .reg = 0x230,
623 .reg = 0x2f0,
625 .mask = 0xff,
626 .def = 0x50,
629 .id = 0x60,
633 .reg = 0x234,
634 .bit = 0,
637 .reg = 0x3b8,
638 .shift = 0,
639 .mask = 0xff,
640 .def = 0x49,
643 .id = 0x61,
647 .reg = 0x234,
651 .reg = 0x3bc,
652 .shift = 0,
653 .mask = 0xff,
654 .def = 0x49,
657 .id = 0x62,
661 .reg = 0x234,
665 .reg = 0x3c0,
666 .shift = 0,
667 .mask = 0xff,
668 .def = 0x49,
671 .id = 0x63,
675 .reg = 0x234,
679 .reg = 0x3c4,
680 .shift = 0,
681 .mask = 0xff,
682 .def = 0x49,
685 .id = 0x64,
689 .reg = 0x234,
693 .reg = 0x3b8,
695 .mask = 0xff,
696 .def = 0x80,
699 .id = 0x65,
703 .reg = 0x234,
707 .reg = 0x3bc,
709 .mask = 0xff,
710 .def = 0x80,
713 .id = 0x66,
717 .reg = 0x234,
721 .reg = 0x3c0,
723 .mask = 0xff,
724 .def = 0x80,
727 .id = 0x67,
731 .reg = 0x234,
735 .reg = 0x3c4,
737 .mask = 0xff,
738 .def = 0x80,
741 .id = 0x6c,
745 .reg = 0x234,
749 .reg = 0x394,
750 .shift = 0,
751 .mask = 0xff,
752 .def = 0x1a,
755 .id = 0x6d,
759 .reg = 0x234,
763 .reg = 0x394,
765 .mask = 0xff,
766 .def = 0x80,
769 .id = 0x72,
773 .reg = 0x234,
777 .reg = 0x398,
778 .shift = 0,
779 .mask = 0xff,
780 .def = 0x80,
783 .id = 0x73,
787 .reg = 0x234,
791 .reg = 0x3c8,
792 .shift = 0,
793 .mask = 0xff,
794 .def = 0x50,
797 .id = 0x78,
801 .reg = 0x234,
805 .reg = 0x3d8,
806 .shift = 0,
807 .mask = 0xff,
808 .def = 0x23,
811 .id = 0x79,
815 .reg = 0x234,
819 .reg = 0x3d8,
821 .mask = 0xff,
822 .def = 0x80,
825 .id = 0x7a,
829 .reg = 0x234,
833 .reg = 0x3dc,
834 .shift = 0,
835 .mask = 0xff,
836 .def = 0xff,
839 .id = 0x7b,
843 .reg = 0x234,
847 .reg = 0x3dc,
848 .shift = 0,
849 .mask = 0xff,
850 .def = 0x80,
853 .id = 0x7e,
857 .reg = 0x234,
861 .reg = 0x3e4,
862 .shift = 0,
863 .mask = 0xff,
864 .def = 0x23,
867 .id = 0x7f,
871 .reg = 0x234,
875 .reg = 0x3e4,
877 .mask = 0xff,
878 .def = 0x80,
881 .id = 0x80,
885 .reg = 0xb98,
886 .bit = 0,
889 .reg = 0x3e0,
890 .shift = 0,
891 .mask = 0xff,
892 .def = 0x2e,
895 .id = 0x81,
899 .reg = 0xb98,
903 .reg = 0xb98,
905 .mask = 0xff,
906 .def = 0x80,
909 .id = 0x82,
913 .reg = 0xb98,
917 .reg = 0x3a0,
918 .shift = 0,
919 .mask = 0xff,
920 .def = 0xff,
923 .id = 0x83,
927 .reg = 0xb98,
931 .reg = 0x3a0,
933 .mask = 0xff,
934 .def = 0x80,
937 .id = 0x84,
941 .reg = 0xb98,
945 .reg = 0x3ec,
946 .shift = 0,
947 .mask = 0xff,
948 .def = 0xff,
951 .id = 0x85,
955 .reg = 0xb98,
959 .reg = 0x3ec,
961 .mask = 0xff,
962 .def = 0xff,
965 .id = 0x86,
969 .reg = 0xb98,
973 .reg = 0x3f0,
974 .shift = 0,
975 .mask = 0xff,
976 .def = 0x9b,
979 .id = 0x87,
983 .reg = 0xb98,
987 .reg = 0x3f0,
989 .mask = 0xff,
990 .def = 0x80,
993 .id = 0x88,
998 .reg = 0xb98,
1002 .reg = 0x3e8,
1003 .shift = 0,
1004 .mask = 0xff,
1005 .def = 0x1a,
1008 .id = 0x89,
1013 .reg = 0xb98,
1017 .reg = 0x3e8,
1019 .mask = 0xff,
1020 .def = 0x80,
1026 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1027 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1028 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1029 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1030 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1031 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1032 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1033 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1034 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1035 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1036 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1037 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1038 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1039 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1040 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1041 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1042 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1043 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1044 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1045 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1046 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1047 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1048 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1049 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1050 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1051 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1052 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1053 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1054 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1093 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1094 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1095 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1096 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1097 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1098 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1099 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1100 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1101 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1102 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1103 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1104 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1105 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1106 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1107 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1108 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1109 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1110 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1111 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1112 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1113 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1114 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1115 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1116 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1117 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1118 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1119 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1120 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1121 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1122 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1130 .client_id_mask = 0xff,