Lines Matching +full:reg +full:- +full:shift
9 #include <dt-bindings/memory/tegra210-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
56 .shift = 16,
65 .reg = 0x228,
69 .reg = 0x2f4,
70 .shift = 16,
79 .reg = 0x228,
83 .reg = 0x2ec,
84 .shift = 0,
93 .reg = 0x228,
97 .reg = 0x2f8,
98 .shift = 0,
107 .reg = 0x228,
111 .reg = 0x2e0,
112 .shift = 0,
121 .reg = 0x228,
125 .reg = 0x2e4,
126 .shift = 0,
135 .reg = 0x228,
139 .reg = 0x2f0,
140 .shift = 0,
149 .reg = 0x228,
153 .reg = 0x2fc,
154 .shift = 0,
163 .reg = 0x228,
167 .reg = 0x318,
168 .shift = 0,
177 .reg = 0x228,
181 .reg = 0x310,
182 .shift = 0,
191 .reg = 0x228,
195 .reg = 0x310,
196 .shift = 16,
205 .reg = 0x228,
209 .reg = 0x328,
210 .shift = 0,
219 .reg = 0x228,
223 .reg = 0x344,
224 .shift = 0,
233 .reg = 0x228,
237 .reg = 0x344,
238 .shift = 16,
247 .reg = 0x228,
251 .reg = 0x350,
252 .shift = 0,
261 .reg = 0x320,
262 .shift = 0,
271 .reg = 0x22c,
275 .reg = 0x328,
276 .shift = 16,
285 .reg = 0x22c,
289 .reg = 0x2e0,
290 .shift = 16,
299 .reg = 0x22c,
303 .reg = 0x2e4,
304 .shift = 16,
313 .reg = 0x22c,
317 .reg = 0x318,
318 .shift = 16,
327 .reg = 0x22c,
331 .reg = 0x314,
332 .shift = 0,
341 .reg = 0x320,
342 .shift = 16,
351 .reg = 0x22c,
355 .reg = 0x348,
356 .shift = 0,
365 .reg = 0x22c,
369 .reg = 0x348,
370 .shift = 16,
379 .reg = 0x22c,
383 .reg = 0x350,
384 .shift = 16,
393 .reg = 0x230,
397 .reg = 0x370,
398 .shift = 0,
407 .reg = 0x230,
411 .reg = 0x374,
412 .shift = 0,
421 .reg = 0x230,
425 .reg = 0x374,
426 .shift = 16,
435 .reg = 0x230,
439 .reg = 0x37c,
440 .shift = 0,
449 .reg = 0x230,
453 .reg = 0x37c,
454 .shift = 16,
463 .reg = 0x230,
467 .reg = 0x380,
468 .shift = 0,
477 .reg = 0x230,
481 .reg = 0x380,
482 .shift = 16,
491 .reg = 0x230,
495 .reg = 0x384,
496 .shift = 0,
505 .reg = 0x230,
509 .reg = 0x388,
510 .shift = 0,
519 .reg = 0x230,
523 .reg = 0x388,
524 .shift = 16,
533 .reg = 0x230,
537 .reg = 0x390,
538 .shift = 0,
547 .reg = 0x230,
551 .reg = 0x390,
552 .shift = 16,
561 .reg = 0x230,
565 .reg = 0x3a4,
566 .shift = 0,
575 .reg = 0x230,
579 .reg = 0x3a4,
580 .shift = 16,
589 /* read-only */
590 .reg = 0x230,
594 .reg = 0x3c8,
595 .shift = 0,
604 /* read-only */
605 .reg = 0x230,
609 .reg = 0x3c8,
610 .shift = 16,
619 .reg = 0x230,
623 .reg = 0x2f0,
624 .shift = 16,
633 .reg = 0x234,
637 .reg = 0x3b8,
638 .shift = 0,
647 .reg = 0x234,
651 .reg = 0x3bc,
652 .shift = 0,
661 .reg = 0x234,
665 .reg = 0x3c0,
666 .shift = 0,
675 .reg = 0x234,
679 .reg = 0x3c4,
680 .shift = 0,
689 .reg = 0x234,
693 .reg = 0x3b8,
694 .shift = 16,
703 .reg = 0x234,
707 .reg = 0x3bc,
708 .shift = 16,
717 .reg = 0x234,
721 .reg = 0x3c0,
722 .shift = 16,
731 .reg = 0x234,
735 .reg = 0x3c4,
736 .shift = 16,
745 .reg = 0x234,
749 .reg = 0x394,
750 .shift = 0,
759 .reg = 0x234,
763 .reg = 0x394,
764 .shift = 16,
773 .reg = 0x234,
777 .reg = 0x398,
778 .shift = 0,
787 .reg = 0x234,
791 .reg = 0x3c8,
792 .shift = 0,
801 .reg = 0x234,
805 .reg = 0x3d8,
806 .shift = 0,
815 .reg = 0x234,
819 .reg = 0x3d8,
820 .shift = 16,
829 .reg = 0x234,
833 .reg = 0x3dc,
834 .shift = 0,
843 .reg = 0x234,
847 .reg = 0x3dc,
848 .shift = 0,
857 .reg = 0x234,
861 .reg = 0x3e4,
862 .shift = 0,
871 .reg = 0x234,
875 .reg = 0x3e4,
876 .shift = 16,
885 .reg = 0xb98,
889 .reg = 0x3e0,
890 .shift = 0,
899 .reg = 0xb98,
903 .reg = 0xb98,
904 .shift = 16,
913 .reg = 0xb98,
917 .reg = 0x3a0,
918 .shift = 0,
927 .reg = 0xb98,
931 .reg = 0x3a0,
932 .shift = 16,
941 .reg = 0xb98,
945 .reg = 0x3ec,
946 .shift = 0,
955 .reg = 0xb98,
959 .reg = 0x3ec,
960 .shift = 16,
969 .reg = 0xb98,
973 .reg = 0x3f0,
974 .shift = 0,
983 .reg = 0xb98,
987 .reg = 0x3f0,
988 .shift = 16,
997 /* read-only */
998 .reg = 0xb98,
1002 .reg = 0x3e8,
1003 .shift = 0,
1012 /* read-only */
1013 .reg = 0xb98,
1017 .reg = 0x3e8,
1018 .shift = 16,
1026 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1027 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1028 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1029 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1030 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1031 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1032 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1033 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1034 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1035 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1036 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1037 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1038 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1039 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1040 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1041 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1042 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1043 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1044 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1045 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1046 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1047 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1048 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1049 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1050 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1051 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1052 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1053 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1054 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },