Lines Matching +full:0 +full:x228
18 .id = 0x00,
22 .id = 0x01,
26 .reg = 0x228,
30 .reg = 0x2e8,
31 .shift = 0,
32 .mask = 0xff,
33 .def = 0x4e,
36 .id = 0x02,
40 .reg = 0x228,
44 .reg = 0x2f4,
45 .shift = 0,
46 .mask = 0xff,
47 .def = 0x4e,
50 .id = 0x03,
54 .reg = 0x228,
58 .reg = 0x2e8,
60 .mask = 0xff,
61 .def = 0x4e,
64 .id = 0x04,
68 .reg = 0x228,
72 .reg = 0x2f4,
74 .mask = 0xff,
75 .def = 0x4e,
78 .id = 0x05,
82 .reg = 0x228,
86 .reg = 0x2ec,
87 .shift = 0,
88 .mask = 0xff,
89 .def = 0x4e,
92 .id = 0x06,
96 .reg = 0x228,
100 .reg = 0x2f8,
101 .shift = 0,
102 .mask = 0xff,
103 .def = 0x4e,
106 .id = 0x07,
110 .reg = 0x228,
114 .reg = 0x2ec,
116 .mask = 0xff,
117 .def = 0x4e,
120 .id = 0x08,
124 .reg = 0x228,
128 .reg = 0x2f8,
130 .mask = 0xff,
131 .def = 0x4e,
134 .id = 0x09,
138 .reg = 0x228,
142 .reg = 0x300,
143 .shift = 0,
144 .mask = 0xff,
145 .def = 0x17,
148 .id = 0x0a,
152 .reg = 0x228,
156 .reg = 0x308,
157 .shift = 0,
158 .mask = 0xff,
159 .def = 0x09,
162 .id = 0x0b,
166 .reg = 0x228,
170 .reg = 0x308,
172 .mask = 0xff,
173 .def = 0x09,
176 .id = 0x0c,
180 .reg = 0x228,
184 .reg = 0x328,
185 .shift = 0,
186 .mask = 0xff,
187 .def = 0x50,
190 .id = 0x0d,
194 .reg = 0x228,
198 .reg = 0x364,
199 .shift = 0,
200 .mask = 0xff,
201 .def = 0x2c,
204 .id = 0x0e,
208 .reg = 0x228,
212 .reg = 0x2e0,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x10,
218 .id = 0x0f,
222 .reg = 0x228,
226 .reg = 0x2e4,
227 .shift = 0,
228 .mask = 0xff,
229 .def = 0x04,
232 .id = 0x10,
236 .reg = 0x228,
240 .reg = 0x2f0,
241 .shift = 0,
242 .mask = 0xff,
243 .def = 0xff,
246 .id = 0x11,
250 .reg = 0x228,
254 .reg = 0x2fc,
255 .shift = 0,
256 .mask = 0xff,
257 .def = 0xff,
260 .id = 0x12,
264 .reg = 0x228,
268 .reg = 0x334,
269 .shift = 0,
270 .mask = 0xff,
271 .def = 0x0a,
274 .id = 0x13,
278 .reg = 0x228,
282 .reg = 0x33c,
283 .shift = 0,
284 .mask = 0xff,
285 .def = 0x0a,
288 .id = 0x14,
292 .reg = 0x228,
296 .reg = 0x30c,
297 .shift = 0,
298 .mask = 0xff,
299 .def = 0x0a,
302 .id = 0x15,
306 .reg = 0x228,
310 .reg = 0x318,
311 .shift = 0,
312 .mask = 0xff,
313 .def = 0xff,
316 .id = 0x16,
320 .reg = 0x228,
324 .reg = 0x310,
325 .shift = 0,
326 .mask = 0xff,
327 .def = 0x05,
330 .id = 0x17,
334 .reg = 0x228,
338 .reg = 0x310,
340 .mask = 0xff,
341 .def = 0x50,
344 .id = 0x18,
348 .reg = 0x228,
352 .reg = 0x334,
354 .mask = 0xff,
355 .def = 0x13,
358 .id = 0x19,
362 .reg = 0x228,
366 .reg = 0x33c,
368 .mask = 0xff,
369 .def = 0x13,
372 .id = 0x1a,
376 .reg = 0x228,
380 .reg = 0x328,
382 .mask = 0xff,
383 .def = 0x80,
386 .id = 0x1b,
390 .reg = 0x228,
394 .reg = 0x32c,
395 .shift = 0,
396 .mask = 0xff,
397 .def = 0x42,
400 .id = 0x1c,
404 .reg = 0x228,
408 .reg = 0x32c,
410 .mask = 0xff,
411 .def = 0xff,
414 .id = 0x1d,
418 .reg = 0x228,
422 .reg = 0x344,
423 .shift = 0,
424 .mask = 0xff,
425 .def = 0x10,
428 .id = 0x1e,
432 .reg = 0x228,
436 .reg = 0x344,
438 .mask = 0xff,
439 .def = 0x12,
442 .id = 0x1f,
446 .reg = 0x228,
450 .reg = 0x350,
451 .shift = 0,
452 .mask = 0xff,
453 .def = 0x33,
456 .id = 0x20,
460 .reg = 0x22c,
461 .bit = 0,
464 .reg = 0x338,
465 .shift = 0,
466 .mask = 0xff,
467 .def = 0x13,
470 .id = 0x21,
474 .reg = 0x22c,
478 .reg = 0x340,
479 .shift = 0,
480 .mask = 0xff,
481 .def = 0x13,
484 .id = 0x22,
488 .reg = 0x22c,
492 .reg = 0x354,
493 .shift = 0,
494 .mask = 0xff,
495 .def = 0xff,
498 .id = 0x23,
502 .reg = 0x22c,
506 .reg = 0x354,
508 .mask = 0xff,
509 .def = 0xd0,
512 .id = 0x24,
516 .reg = 0x22c,
520 .reg = 0x358,
521 .shift = 0,
522 .mask = 0xff,
523 .def = 0x2a,
526 .id = 0x25,
530 .reg = 0x22c,
534 .reg = 0x358,
536 .mask = 0xff,
537 .def = 0x74,
540 .id = 0x26,
544 .reg = 0x324,
545 .shift = 0,
546 .mask = 0xff,
547 .def = 0x04,
550 .id = 0x27,
554 .reg = 0x320,
555 .shift = 0,
556 .mask = 0xff,
557 .def = 0x04,
560 .id = 0x28,
564 .reg = 0x22c,
568 .reg = 0x300,
570 .mask = 0xff,
571 .def = 0x6c,
574 .id = 0x29,
578 .reg = 0x22c,
582 .reg = 0x304,
583 .shift = 0,
584 .mask = 0xff,
585 .def = 0x6c,
588 .id = 0x2a,
592 .reg = 0x22c,
596 .reg = 0x304,
598 .mask = 0xff,
599 .def = 0x6c,
602 .id = 0x2b,
606 .reg = 0x22c,
610 .reg = 0x330,
611 .shift = 0,
612 .mask = 0xff,
613 .def = 0x13,
616 .id = 0x2c,
620 .reg = 0x22c,
624 .reg = 0x364,
626 .mask = 0xff,
627 .def = 0x12,
630 .id = 0x2d,
634 .reg = 0x22c,
638 .reg = 0x368,
639 .shift = 0,
640 .mask = 0xff,
641 .def = 0xb2,
644 .id = 0x2e,
648 .reg = 0x22c,
652 .reg = 0x368,
654 .mask = 0xff,
655 .def = 0xb2,
658 .id = 0x2f,
662 .reg = 0x22c,
666 .reg = 0x36c,
667 .shift = 0,
668 .mask = 0xff,
669 .def = 0x12,
672 .id = 0x30,
676 .reg = 0x22c,
680 .reg = 0x30c,
682 .mask = 0xff,
683 .def = 0x9,
686 .id = 0x31,
690 .reg = 0x22c,
694 .reg = 0x2e0,
696 .mask = 0xff,
697 .def = 0x0c,
700 .id = 0x32,
704 .reg = 0x22c,
708 .reg = 0x2e4,
710 .mask = 0xff,
711 .def = 0x0e,
714 .id = 0x33,
718 .reg = 0x22c,
722 .reg = 0x338,
724 .mask = 0xff,
725 .def = 0x0a,
728 .id = 0x34,
732 .reg = 0x22c,
736 .reg = 0x340,
738 .mask = 0xff,
739 .def = 0x0a,
742 .id = 0x35,
746 .reg = 0x22c,
750 .reg = 0x318,
752 .mask = 0xff,
753 .def = 0xff,
756 .id = 0x36,
760 .reg = 0x22c,
764 .reg = 0x314,
765 .shift = 0,
766 .mask = 0xff,
767 .def = 0x10,
770 .id = 0x37,
774 .reg = 0x22c,
778 .reg = 0x31c,
779 .shift = 0,
780 .mask = 0xff,
781 .def = 0xff,
784 .id = 0x38,
788 .reg = 0x324,
790 .mask = 0xff,
791 .def = 0x0e,
794 .id = 0x39,
798 .reg = 0x320,
800 .mask = 0xff,
801 .def = 0x0e,
804 .id = 0x3a,
808 .reg = 0x22c,
812 .reg = 0x330,
814 .mask = 0xff,
815 .def = 0xff,
818 .id = 0x3b,
822 .reg = 0x22c,
826 .reg = 0x348,
827 .shift = 0,
828 .mask = 0xff,
829 .def = 0x10,
832 .id = 0x3c,
836 .reg = 0x22c,
840 .reg = 0x348,
842 .mask = 0xff,
843 .def = 0x06,
846 .id = 0x3d,
850 .reg = 0x22c,
854 .reg = 0x350,
856 .mask = 0xff,
857 .def = 0x33,
860 .id = 0x3e,
864 .reg = 0x22c,
868 .reg = 0x35c,
869 .shift = 0,
870 .mask = 0xff,
871 .def = 0xff,
874 .id = 0x3f,
878 .reg = 0x22c,
882 .reg = 0x35c,
884 .mask = 0xff,
885 .def = 0xff,
888 .id = 0x40,
892 .reg = 0x230,
893 .bit = 0,
896 .reg = 0x360,
897 .shift = 0,
898 .mask = 0xff,
899 .def = 0x42,
902 .id = 0x41,
906 .reg = 0x230,
910 .reg = 0x360,
912 .mask = 0xff,
913 .def = 0x2a,
919 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
920 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
921 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
922 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
923 { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
924 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
925 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
926 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
927 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
928 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
929 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
930 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
931 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
932 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
933 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
934 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
973 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
974 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
975 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
976 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
977 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
978 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
979 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
980 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
981 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
982 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
983 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
984 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
985 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
986 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
987 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
988 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
989 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
990 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
998 .client_id_mask = 0x7f,