Lines Matching full:r1
56 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
57 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
59 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
60 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
62 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
63 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
65 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
66 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
68 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
69 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
71 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
72 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
74 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
75 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
77 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
78 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
80 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
81 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
83 ldr r1, [r0, #EMIF_COS_CONFIG]
84 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
86 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
87 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
89 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
90 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
92 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
93 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
95 ldr r1, [r0, #EMIF_OCP_CONFIG]
96 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
102 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
103 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
105 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
106 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
108 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
109 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
111 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
112 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
114 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
115 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
117 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
118 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
125 ldr r1, [r3, r5]
126 str r1, [r4, r5]
148 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
149 str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
150 str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
152 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
153 str r1, [r0, #EMIF_SDRAM_TIMING_1]
154 str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
156 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
157 str r1, [r0, #EMIF_SDRAM_TIMING_2]
158 str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
160 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
161 str r1, [r0, #EMIF_SDRAM_TIMING_3]
162 str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
164 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
165 str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
166 str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
168 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
169 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
171 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
172 str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
174 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
175 str r1, [r0, #EMIF_COS_CONFIG]
177 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
178 str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
180 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
181 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
183 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
184 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
186 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
187 str r1, [r0, #EMIF_OCP_CONFIG]
193 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
194 str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
196 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
197 str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
199 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
200 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
202 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
203 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
205 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
206 str r1, [r0, #EMIF_DLL_CALIB_CTRL]
208 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
209 str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
211 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
212 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
222 ldr r1, [r3, r5]
223 str r1, [r4, r5]
235 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
236 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
239 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
240 and r2, r1, #SDRAM_TYPE_MASK
242 streq r1, [r0, #EMIF_SDRAM_CONFIG]
261 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
262 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
263 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
264 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
289 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
290 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
291 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
292 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
293 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
294 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
297 1: ldr r1, [r0, #EMIF_STATUS]
298 tst r1, #EMIF_STATUS_READY
318 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
319 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
320 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
323 1: ldr r1, [r0, #EMIF_STATUS]
324 tst r1, #EMIF_STATUS_READY