Lines Matching full:63
186 #define CXL_PSL_Control_tb (0x1ull << (63-63))
187 #define CXL_PSL_Control_Fr (0x1ull << (63-31))
188 #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
189 #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
192 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
193 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
194 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
195 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
201 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
203 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
204 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
205 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
206 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
208 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
209 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
210 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
211 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
213 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
214 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
217 #define CXL_PSL_ID_An_F (1ull << (63-31))
218 #define CXL_PSL_ID_An_L (1ull << (63-30))
221 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
222 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
223 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
224 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
225 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
226 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
227 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
228 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
229 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
234 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
235 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
236 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
237 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
238 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
239 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
240 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
241 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
242 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
248 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
251 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
253 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
254 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
255 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
256 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
257 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
258 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
260 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
261 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
262 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
264 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
266 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
267 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
268 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
270 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
273 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
274 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
275 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
277 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
279 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
280 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
281 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
283 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
288 #define CXL_SSTP0_An_KS (1ull << (63-2))
289 #define CXL_SSTP0_An_KP (1ull << (63-3))
290 #define CXL_SSTP0_An_N (1ull << (63-4))
291 #define CXL_SSTP0_An_L (1ull << (63-5))
292 #define CXL_SSTP0_An_C (1ull << (63-6))
293 #define CXL_SSTP0_An_TA (1ull << (63-7))
294 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
296 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
299 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
300 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
301 #define CXL_SSTP1_An_V (1ull << (63-63))
311 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
322 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
325 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
326 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
327 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
328 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
330 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
331 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
332 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
334 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
337 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibite…
342 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
343 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
344 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
345 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
346 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
349 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
362 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
363 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
364 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
365 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
368 #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
371 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
372 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
373 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
374 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
375 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
376 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */