Lines Matching +full:native +full:- +full:mode
22 #include <asm/pnv-pci.h>
93 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
94 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
174 dev_info(&dev->dev, "dump_cxl_config_space\n"); in dump_cxl_config_space()
177 dev_info(&dev->dev, "BAR0: %#.8x\n", val); in dump_cxl_config_space()
179 dev_info(&dev->dev, "BAR1: %#.8x\n", val); in dump_cxl_config_space()
181 dev_info(&dev->dev, "BAR2: %#.8x\n", val); in dump_cxl_config_space()
183 dev_info(&dev->dev, "BAR3: %#.8x\n", val); in dump_cxl_config_space()
185 dev_info(&dev->dev, "BAR4: %#.8x\n", val); in dump_cxl_config_space()
187 dev_info(&dev->dev, "BAR5: %#.8x\n", val); in dump_cxl_config_space()
189 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", in dump_cxl_config_space()
191 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", in dump_cxl_config_space()
193 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", in dump_cxl_config_space()
200 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) in dump_cxl_config_space()
213 show_reg("Mode Control", (val >> 16) & 0xff); in dump_cxl_config_space()
278 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) in dump_afu_descriptor()
295 show_reg("Reserved", (val >> (63-7)) & 0xff); in dump_afu_descriptor()
304 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); in dump_afu_descriptor()
311 show_reg("Reserved", (val >> (63-7)) & 0xff); in dump_afu_descriptor()
332 if (of_property_read_u32(np, "ibm,phb-index", phb_index)) in get_phb_index()
333 return -ENODEV; in get_phb_index()
341 * - For chips other than POWER8NVL, we only have CAPP 0, in get_capp_unit_id()
343 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and in get_capp_unit_id()
360 * PEC1 (PHB1 - PHB2). No capi mode in get_capp_unit_id()
361 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000) in get_capp_unit_id()
382 return -ENODEV; in cxl_calc_capp_routing()
384 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) in cxl_calc_capp_routing()
387 return -ENODEV; in cxl_calc_capp_routing()
400 …pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible sl… in cxl_calc_capp_routing()
402 return -ENODEV; in cxl_calc_capp_routing()
421 return -ENODEV; in get_phb_indications()
424 prop = of_get_property(np, "ibm,phb-indications", NULL); in get_phb_indications()
450 * bit 61:60 MSI bits --> 0 in cxl_get_xsl9_dsnctl()
451 * bit 59 TVT selector --> 0 in cxl_get_xsl9_dsnctl()
454 return -ENODEV; in cxl_get_xsl9_dsnctl()
460 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */ in cxl_get_xsl9_dsnctl()
461 xsl_dsnctl |= (capp_unit_id << (63-15)); in cxl_get_xsl9_dsnctl()
464 xsl_dsnctl |= ((u64)0x09 << (63-28)); in cxl_get_xsl9_dsnctl()
468 * the Non-Blocking queues by the PHB. This field should match in cxl_get_xsl9_dsnctl()
473 xsl_dsnctl |= (nbwind << (63-55)); in cxl_get_xsl9_dsnctl()
507 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ in init_implementation_adapter_regs_psl9()
508 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ in init_implementation_adapter_regs_psl9()
531 /* disable machines 31-47 and 20-27 for DMA */ in init_implementation_adapter_regs_psl9()
542 * Check if PSL has data-cache. We need to flush adapter datacache in init_implementation_adapter_regs_psl9()
547 dev_dbg(&dev->dev, "No data-cache present\n"); in init_implementation_adapter_regs_psl9()
548 adapter->native->no_data_cache = true; in init_implementation_adapter_regs_psl9()
567 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */ in init_implementation_adapter_regs_psl8()
569 psl_dsnctl |= (chipid << (63-5)); in init_implementation_adapter_regs_psl8()
570 psl_dsnctl |= (capp_unit_id << (63-13)); in init_implementation_adapter_regs_psl8()
577 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */ in init_implementation_adapter_regs_psl8()
578 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */ in init_implementation_adapter_regs_psl8()
588 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
589 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
613 adapter->psl_timebase_synced = false; in cxl_setup_psl_timebase()
620 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { in cxl_setup_psl_timebase()
622 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); in cxl_setup_psl_timebase()
631 if (adapter->native->sl_ops->write_timebase_ctrl) in cxl_setup_psl_timebase()
632 adapter->native->sl_ops->write_timebase_ctrl(adapter); in cxl_setup_psl_timebase()
662 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_setup_irq()
669 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_update_image_control()
675 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in cxl_update_image_control()
676 return -ENODEV; in cxl_update_image_control()
680 dev_err(&dev->dev, "failed to read image state: %i\n", rc); in cxl_update_image_control()
684 if (adapter->perst_loads_image) in cxl_update_image_control()
689 if (adapter->perst_select_user) in cxl_update_image_control()
695 dev_err(&dev->dev, "failed to update image control: %i\n", rc); in cxl_update_image_control()
704 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_alloc_one_irq()
711 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_release_one_irq()
719 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_alloc_irq_ranges()
727 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_release_irq_ranges()
737 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); in setup_cxl_bars()
738 return -ENODEV; in setup_cxl_bars()
752 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
759 dev_info(&dev->dev, "switch card to CXL\n"); in switch_card_to_cxl()
762 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in switch_card_to_cxl()
763 return -ENODEV; in switch_card_to_cxl()
767 dev_err(&dev->dev, "failed to read current mode control: %i", rc); in switch_card_to_cxl()
773 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); in switch_card_to_cxl()
777 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states in switch_card_to_cxl()
778 * we must wait 100ms after this mode switch before touching in switch_card_to_cxl()
792 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); in pci_map_slice_regs()
793 p2n_base = p2_base(dev) + (afu->slice * p2n_size); in pci_map_slice_regs()
794 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); in pci_map_slice_regs()
795 …afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_… in pci_map_slice_regs()
797 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) in pci_map_slice_regs()
799 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) in pci_map_slice_regs()
802 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) in pci_map_slice_regs()
808 iounmap(afu->p2n_mmio); in pci_map_slice_regs()
810 iounmap(afu->native->p1n_mmio); in pci_map_slice_regs()
812 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); in pci_map_slice_regs()
813 return -ENOMEM; in pci_map_slice_regs()
818 if (afu->p2n_mmio) { in pci_unmap_slice_regs()
819 iounmap(afu->p2n_mmio); in pci_unmap_slice_regs()
820 afu->p2n_mmio = NULL; in pci_unmap_slice_regs()
822 if (afu->native->p1n_mmio) { in pci_unmap_slice_regs()
823 iounmap(afu->native->p1n_mmio); in pci_unmap_slice_regs()
824 afu->native->p1n_mmio = NULL; in pci_unmap_slice_regs()
826 if (afu->native->afu_desc_mmio) { in pci_unmap_slice_regs()
827 iounmap(afu->native->afu_desc_mmio); in pci_unmap_slice_regs()
828 afu->native->afu_desc_mmio = NULL; in pci_unmap_slice_regs()
838 idr_destroy(&afu->contexts_idr); in cxl_pci_release_afu()
841 kfree(afu->native); in cxl_pci_release_afu()
851 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); in cxl_read_afu_descriptor()
852 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); in cxl_read_afu_descriptor()
853 afu->crs_num = AFUD_NUM_CRS(val); in cxl_read_afu_descriptor()
856 afu->modes_supported |= CXL_MODE_DIRECTED; in cxl_read_afu_descriptor()
858 afu->modes_supported |= CXL_MODE_DEDICATED; in cxl_read_afu_descriptor()
860 afu->modes_supported |= CXL_MODE_TIME_SLICED; in cxl_read_afu_descriptor()
863 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; in cxl_read_afu_descriptor()
864 afu->psa = AFUD_PPPSA_PSA(val); in cxl_read_afu_descriptor()
865 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) in cxl_read_afu_descriptor()
866 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); in cxl_read_afu_descriptor()
869 afu->crs_len = AFUD_CR_LEN(val) * 256; in cxl_read_afu_descriptor()
870 afu->crs_offset = AFUD_READ_CR_OFF(afu); in cxl_read_afu_descriptor()
874 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; in cxl_read_afu_descriptor()
875 afu->eb_offset = AFUD_READ_EB_OFF(afu); in cxl_read_afu_descriptor()
878 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { in cxl_read_afu_descriptor()
879 dev_warn(&afu->dev, in cxl_read_afu_descriptor()
881 afu->eb_offset); in cxl_read_afu_descriptor()
882 dev_info(&afu->dev, in cxl_read_afu_descriptor()
885 afu->eb_len = 0; in cxl_read_afu_descriptor()
896 if (afu->psa && afu->adapter->ps_size < in cxl_afu_descriptor_looks_ok()
897 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { in cxl_afu_descriptor_looks_ok()
898 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); in cxl_afu_descriptor_looks_ok()
899 return -ENODEV; in cxl_afu_descriptor_looks_ok()
902 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) in cxl_afu_descriptor_looks_ok()
903 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size); in cxl_afu_descriptor_looks_ok()
905 for (i = 0; i < afu->crs_num; i++) { in cxl_afu_descriptor_looks_ok()
906 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); in cxl_afu_descriptor_looks_ok()
908 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); in cxl_afu_descriptor_looks_ok()
909 return -EINVAL; in cxl_afu_descriptor_looks_ok()
913 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) { in cxl_afu_descriptor_looks_ok()
924 dev_err(&afu->dev, "AFU does not support any processes\n"); in cxl_afu_descriptor_looks_ok()
925 return -EINVAL; in cxl_afu_descriptor_looks_ok()
942 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); in sanitise_afu_regs_psl9()
943 if (cxl_ops->afu_reset(afu)) in sanitise_afu_regs_psl9()
944 return -EIO; in sanitise_afu_regs_psl9()
946 return -EIO; in sanitise_afu_regs_psl9()
948 return -EIO; in sanitise_afu_regs_psl9()
954 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); in sanitise_afu_regs_psl9()
960 if (afu->adapter->native->sl_ops->register_serr_irq) { in sanitise_afu_regs_psl9()
964 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); in sanitise_afu_regs_psl9()
970 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); in sanitise_afu_regs_psl9()
988 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); in sanitise_afu_regs_psl8()
989 if (cxl_ops->afu_reset(afu)) in sanitise_afu_regs_psl8()
990 return -EIO; in sanitise_afu_regs_psl8()
992 return -EIO; in sanitise_afu_regs_psl8()
994 return -EIO; in sanitise_afu_regs_psl8()
1009 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1015 if (afu->adapter->native->sl_ops->register_serr_irq) { in sanitise_afu_regs_psl8()
1019 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1025 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); in sanitise_afu_regs_psl8()
1045 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; in cxl_pci_afu_read_err_buffer()
1047 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) in cxl_pci_afu_read_err_buffer()
1051 count = min((size_t)(afu->eb_len - off), count); in cxl_pci_afu_read_err_buffer()
1054 aligned_length = aligned_end - aligned_start; in cxl_pci_afu_read_err_buffer()
1059 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); in cxl_pci_afu_read_err_buffer()
1065 return -ENOMEM; in cxl_pci_afu_read_err_buffer()
1083 if (adapter->native->sl_ops->sanitise_afu_regs) { in pci_configure_afu()
1084 rc = adapter->native->sl_ops->sanitise_afu_regs(afu); in pci_configure_afu()
1090 if ((rc = cxl_ops->afu_reset(afu))) in pci_configure_afu()
1102 if (adapter->native->sl_ops->afu_regs_init) in pci_configure_afu()
1103 if ((rc = adapter->native->sl_ops->afu_regs_init(afu))) in pci_configure_afu()
1106 if (adapter->native->sl_ops->register_serr_irq) in pci_configure_afu()
1107 if ((rc = adapter->native->sl_ops->register_serr_irq(afu))) in pci_configure_afu()
1113 atomic_set(&afu->configured_state, 0); in pci_configure_afu()
1117 if (adapter->native->sl_ops->release_serr_irq) in pci_configure_afu()
1118 adapter->native->sl_ops->release_serr_irq(afu); in pci_configure_afu()
1130 if (atomic_read(&afu->configured_state) != -1) { in pci_deconfigure_afu()
1131 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1) in pci_deconfigure_afu()
1135 if (afu->adapter->native->sl_ops->release_serr_irq) in pci_deconfigure_afu()
1136 afu->adapter->native->sl_ops->release_serr_irq(afu); in pci_deconfigure_afu()
1143 int rc = -ENOMEM; in pci_init_afu()
1147 return -ENOMEM; in pci_init_afu()
1149 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); in pci_init_afu()
1150 if (!afu->native) in pci_init_afu()
1153 mutex_init(&afu->native->spa_mutex); in pci_init_afu()
1155 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); in pci_init_afu()
1176 adapter->afu[afu->slice] = afu; in pci_init_afu()
1179 dev_info(&afu->dev, "Can't register vPHB\n"); in pci_init_afu()
1186 device_unregister(&afu->dev); in pci_init_afu()
1190 kfree(afu->native); in pci_init_afu()
1208 spin_lock(&afu->adapter->afu_list_lock); in cxl_pci_remove_afu()
1209 afu->adapter->afu[afu->slice] = NULL; in cxl_pci_remove_afu()
1210 spin_unlock(&afu->adapter->afu_list_lock); in cxl_pci_remove_afu()
1213 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); in cxl_pci_remove_afu()
1216 device_unregister(&afu->dev); in cxl_pci_remove_afu()
1221 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_pci_reset()
1224 if (adapter->perst_same_image) { in cxl_pci_reset()
1225 dev_warn(&dev->dev, in cxl_pci_reset()
1227 return -EINVAL; in cxl_pci_reset()
1230 dev_info(&dev->dev, "CXL reset\n"); in cxl_pci_reset()
1241 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); in cxl_pci_reset()
1258 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) in cxl_map_adapter_regs()
1261 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) in cxl_map_adapter_regs()
1267 iounmap(adapter->native->p1_mmio); in cxl_map_adapter_regs()
1268 adapter->native->p1_mmio = NULL; in cxl_map_adapter_regs()
1274 return -ENOMEM; in cxl_map_adapter_regs()
1279 if (adapter->native->p1_mmio) { in cxl_unmap_adapter_regs()
1280 iounmap(adapter->native->p1_mmio); in cxl_unmap_adapter_regs()
1281 adapter->native->p1_mmio = NULL; in cxl_unmap_adapter_regs()
1282 pci_release_region(to_pci_dev(adapter->dev.parent), 2); in cxl_unmap_adapter_regs()
1284 if (adapter->native->p2_mmio) { in cxl_unmap_adapter_regs()
1285 iounmap(adapter->native->p2_mmio); in cxl_unmap_adapter_regs()
1286 adapter->native->p2_mmio = NULL; in cxl_unmap_adapter_regs()
1287 pci_release_region(to_pci_dev(adapter->dev.parent), 0); in cxl_unmap_adapter_regs()
1300 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); in cxl_read_vsec()
1301 return -ENODEV; in cxl_read_vsec()
1306 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); in cxl_read_vsec()
1307 return -EINVAL; in cxl_read_vsec()
1310 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); in cxl_read_vsec()
1311 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); in cxl_read_vsec()
1312 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); in cxl_read_vsec()
1313 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); in cxl_read_vsec()
1314 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); in cxl_read_vsec()
1316 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); in cxl_read_vsec()
1317 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); in cxl_read_vsec()
1318 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE); in cxl_read_vsec()
1320 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); in cxl_read_vsec()
1327 * code a month later and forget what units these are in ;-) */ in cxl_read_vsec()
1328 adapter->native->ps_off = ps_off * 64 * 1024; in cxl_read_vsec()
1329 adapter->ps_size = ps_size * 64 * 1024; in cxl_read_vsec()
1330 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; in cxl_read_vsec()
1331 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; in cxl_read_vsec()
1333 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ in cxl_read_vsec()
1334 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; in cxl_read_vsec()
1352 if (adapter->psl_rev & 0xf000) in cxl_fixup_malformed_tlp()
1367 if (cxl_is_power8() && (adapter->caia_major == 1)) in cxl_compatible_caia_version()
1370 if (cxl_is_power9() && (adapter->caia_major == 2)) in cxl_compatible_caia_version()
1378 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) in cxl_vsec_looks_ok()
1379 return -EBUSY; in cxl_vsec_looks_ok()
1381 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { in cxl_vsec_looks_ok()
1382 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); in cxl_vsec_looks_ok()
1383 return -EINVAL; in cxl_vsec_looks_ok()
1387 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n", in cxl_vsec_looks_ok()
1388 adapter->caia_major); in cxl_vsec_looks_ok()
1389 return -ENODEV; in cxl_vsec_looks_ok()
1392 if (!adapter->slices) { in cxl_vsec_looks_ok()
1395 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); in cxl_vsec_looks_ok()
1396 return -EINVAL; in cxl_vsec_looks_ok()
1399 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { in cxl_vsec_looks_ok()
1400 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); in cxl_vsec_looks_ok()
1401 return -EINVAL; in cxl_vsec_looks_ok()
1404 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { in cxl_vsec_looks_ok()
1405 dev_err(&dev->dev, "ABORTING: Problem state size larger than " in cxl_vsec_looks_ok()
1407 adapter->ps_size, p2_size(dev) - adapter->native->ps_off); in cxl_vsec_looks_ok()
1408 return -EINVAL; in cxl_vsec_looks_ok()
1416 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); in cxl_pci_read_adapter_vpd()
1427 kfree(adapter->native); in cxl_release_adapter()
1431 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1440 if (adapter->native->sl_ops->invalidate_all) { in sanitise_adapter_regs()
1442 if (cxl_is_power9() && (adapter->perst_loads_image)) in sanitise_adapter_regs()
1444 rc = adapter->native->sl_ops->invalidate_all(adapter); in sanitise_adapter_regs()
1457 adapter->dev.parent = &dev->dev; in cxl_configure_adapter()
1458 adapter->dev.release = cxl_release_adapter; in cxl_configure_adapter()
1463 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); in cxl_configure_adapter()
1490 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev))) in cxl_configure_adapter()
1493 /* Required for devices using CAPP DMA mode, harmless for others */ in cxl_configure_adapter()
1496 adapter->tunneled_ops_supported = false; in cxl_configure_adapter()
1500 dev_info(&dev->dev, "Tunneled operations unsupported\n"); in cxl_configure_adapter()
1502 adapter->tunneled_ops_supported = true; in cxl_configure_adapter()
1505 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode))) in cxl_configure_adapter()
1509 * In the non-recovery case this has no effect */ in cxl_configure_adapter()
1529 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); in cxl_deconfigure_adapter()
1544 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); in cxl_stop_trace_psl9()
1549 trace_mask = (0x3ULL << (62 - traceid * 2)); in cxl_stop_trace_psl9()
1550 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2); in cxl_stop_trace_psl9()
1551 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n", in cxl_stop_trace_psl9()
1569 spin_lock(&adapter->afu_list_lock); in cxl_stop_trace_psl8()
1570 for (slice = 0; slice < adapter->slices; slice++) { in cxl_stop_trace_psl8()
1571 if (adapter->afu[slice]) in cxl_stop_trace_psl8()
1572 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE, in cxl_stop_trace_psl8()
1575 spin_unlock(&adapter->afu_list_lock); in cxl_stop_trace_psl8()
1628 dev_info(&dev->dev, "Device uses a PSL8\n"); in set_sl_ops()
1629 adapter->native->sl_ops = &psl8_ops; in set_sl_ops()
1631 dev_info(&dev->dev, "Device uses a PSL9\n"); in set_sl_ops()
1632 adapter->native->sl_ops = &psl9_ops; in set_sl_ops()
1644 return ERR_PTR(-ENOMEM); in cxl_pci_init_adapter()
1646 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); in cxl_pci_init_adapter()
1647 if (!adapter->native) { in cxl_pci_init_adapter()
1648 rc = -ENOMEM; in cxl_pci_init_adapter()
1657 adapter->perst_loads_image = true; in cxl_pci_init_adapter()
1658 adapter->perst_same_image = false; in cxl_pci_init_adapter()
1690 device_unregister(&adapter->dev); in cxl_pci_init_adapter()
1694 cxl_release_adapter(&adapter->dev); in cxl_pci_init_adapter()
1712 device_unregister(&adapter->dev); in cxl_pci_remove_adapter()
1725 return -ENODEV; in cxl_slot_is_switched()
1746 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); in cxl_probe()
1747 return -ENODEV; in cxl_probe()
1751 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n"); in cxl_probe()
1752 return -ENODEV; in cxl_probe()
1756 dev_info(&dev->dev, "Only Radix mode supported\n"); in cxl_probe()
1757 return -ENODEV; in cxl_probe()
1765 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); in cxl_probe()
1769 for (slice = 0; slice < adapter->slices; slice++) { in cxl_probe()
1771 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); in cxl_probe()
1775 rc = cxl_afu_select_best_mode(adapter->afu[slice]); in cxl_probe()
1777 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); in cxl_probe()
1793 for (i = 0; i < adapter->slices; i++) { in cxl_remove()
1794 afu = adapter->afu[i]; in cxl_remove()
1810 if (afu == NULL || afu->phb == NULL) in cxl_vphb_error_detected()
1813 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { in cxl_vphb_error_detected()
1814 if (!afu_dev->driver) in cxl_vphb_error_detected()
1817 afu_dev->error_state = state; in cxl_vphb_error_detected()
1819 if (afu_dev->driver->err_handler) in cxl_vphb_error_detected()
1820 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, in cxl_vphb_error_detected()
1849 spin_lock(&adapter->afu_list_lock); in cxl_pci_error_detected()
1850 for (i = 0; i < adapter->slices; i++) { in cxl_pci_error_detected()
1851 afu = adapter->afu[i]; in cxl_pci_error_detected()
1858 spin_unlock(&adapter->afu_list_lock); in cxl_pci_error_detected()
1865 * different, including a non-CAPI card. As such, by default in cxl_pci_error_detected()
1867 * the slot re-probed. (TODO: check EEH doesn't blindly rebind in cxl_pci_error_detected()
1872 * order to get back to a more reliable known-good state. in cxl_pci_error_detected()
1875 * trust that we'll come back the same - we could have a new in cxl_pci_error_detected()
1878 * back the same - for example a regular EEH event. in cxl_pci_error_detected()
1884 if (adapter->perst_loads_image && !adapter->perst_same_image) { in cxl_pci_error_detected()
1885 /* TODO take the PHB out of CXL mode */ in cxl_pci_error_detected()
1886 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); in cxl_pci_error_detected()
1895 * - We send the driver, if bound, an error_detected callback. in cxl_pci_error_detected()
1900 * - We detach all contexts associated with the AFU. This in cxl_pci_error_detected()
1906 * - We clean up our side: releasing and unmapping resources we hold in cxl_pci_error_detected()
1911 * - Any contexts you create in your kernel driver (except in cxl_pci_error_detected()
1916 * - We will take responsibility for re-initialising the in cxl_pci_error_detected()
1942 spin_lock(&adapter->afu_list_lock); in cxl_pci_error_detected()
1944 for (i = 0; i < adapter->slices; i++) { in cxl_pci_error_detected()
1945 afu = adapter->afu[i]; in cxl_pci_error_detected()
1952 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); in cxl_pci_error_detected()
1962 spin_unlock(&adapter->afu_list_lock); in cxl_pci_error_detected()
1966 dev_warn(&adapter->dev, in cxl_pci_error_detected()
1967 "Couldn't take context lock with %d active-contexts\n", in cxl_pci_error_detected()
1968 atomic_read(&adapter->contexts_num)); in cxl_pci_error_detected()
1995 spin_lock(&adapter->afu_list_lock); in cxl_pci_slot_reset()
1996 for (i = 0; i < adapter->slices; i++) { in cxl_pci_slot_reset()
1997 afu = adapter->afu[i]; in cxl_pci_slot_reset()
2008 if (afu->phb == NULL) in cxl_pci_slot_reset()
2011 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { in cxl_pci_slot_reset()
2024 afu_dev->dev.archdata.cxl_ctx = ctx; in cxl_pci_slot_reset()
2026 if (cxl_ops->afu_check_and_enable(afu)) in cxl_pci_slot_reset()
2029 afu_dev->error_state = pci_channel_io_normal; in cxl_pci_slot_reset()
2037 if (!afu_dev->driver) in cxl_pci_slot_reset()
2040 if (afu_dev->driver->err_handler && in cxl_pci_slot_reset()
2041 afu_dev->driver->err_handler->slot_reset) in cxl_pci_slot_reset()
2042 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); in cxl_pci_slot_reset()
2049 spin_unlock(&adapter->afu_list_lock); in cxl_pci_slot_reset()
2053 spin_unlock(&adapter->afu_list_lock); in cxl_pci_slot_reset()
2060 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); in cxl_pci_slot_reset()
2075 spin_lock(&adapter->afu_list_lock); in cxl_pci_resume()
2076 for (i = 0; i < adapter->slices; i++) { in cxl_pci_resume()
2077 afu = adapter->afu[i]; in cxl_pci_resume()
2079 if (afu == NULL || afu->phb == NULL) in cxl_pci_resume()
2082 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { in cxl_pci_resume()
2083 if (afu_dev->driver && afu_dev->driver->err_handler && in cxl_pci_resume()
2084 afu_dev->driver->err_handler->resume) in cxl_pci_resume()
2085 afu_dev->driver->err_handler->resume(afu_dev); in cxl_pci_resume()
2088 spin_unlock(&adapter->afu_list_lock); in cxl_pci_resume()
2098 .name = "cxl-pci",