Lines Matching +full:2 +full:- +full:point
10 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
13 * it under the terms of version 2 of the GNU General Public License as
31 * linux-mei@linux.intel.com
36 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
105 #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
108 #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
109 #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
110 #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
112 #define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */
113 #define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */
114 #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */
115 #define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */
117 #define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */
118 #define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */
120 #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */
121 #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */
122 #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */
123 #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */
134 #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */
135 #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */
137 #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */
138 #define MEI_DEV_ID_CNP_LP_4 0x9DE4 /* Cannon Point LP 4 (iTouch) */
139 #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */
140 #define MEI_DEV_ID_CNP_H_4 0xA364 /* Cannon Point H 4 (iTouch) */
142 #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */
143 #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */
145 #define MEI_DEV_ID_CMP_V 0xA3BA /* Comet Point Lake V */
152 #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */
154 #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */
173 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
175 /* H_CSR - Host Control Status register */
177 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
179 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
181 /* H_HGC_CSR - PGI register */
183 /* H_D0I3C - D0I3 Control */
187 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
213 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
216 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
218 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
220 /* ME Power Gate Isolation Capability HRA - host ready only access */
222 /* ME Reset HRA - host read only access to ME_RST */
224 /* ME Ready HRA - host read only access to ME_RDY */
226 /* ME Interrupt Generate HRA - host read only access to ME_IG */
228 /* ME Interrupt Status HRA - host read only access to ME_IS */
230 /* ME Interrupt Enable HRA - host read only access to ME_IE */