Lines Matching +full:hw +full:- +full:settle +full:- +full:time
4 * Copyright (c) 2013-2014, Intel Corporation.
28 #include "hw-txe.h"
32 #include "mei-trace.h"
37 * mei_txe_reg_read - Reads 32bit data from the txe device
51 * mei_txe_reg_write - Writes 32bit data to the txe device
64 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
66 * @hw: the txe hardware structure
73 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, in mei_txe_sec_reg_read_silent() argument
76 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); in mei_txe_sec_reg_read_silent()
80 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
82 * @hw: the txe hardware structure
89 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, in mei_txe_sec_reg_read() argument
92 WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); in mei_txe_sec_reg_read()
93 return mei_txe_sec_reg_read_silent(hw, offset); in mei_txe_sec_reg_read()
96 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
99 * @hw: the txe hardware structure
105 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, in mei_txe_sec_reg_write_silent() argument
108 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); in mei_txe_sec_reg_write_silent()
112 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
114 * @hw: the txe hardware structure
120 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, in mei_txe_sec_reg_write() argument
123 WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); in mei_txe_sec_reg_write()
124 mei_txe_sec_reg_write_silent(hw, offset, value); in mei_txe_sec_reg_write()
127 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
129 * @hw: the txe hardware structure
134 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, in mei_txe_br_reg_read() argument
137 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); in mei_txe_br_reg_read()
141 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
143 * @hw: the txe hardware structure
147 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, in mei_txe_br_reg_write() argument
150 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); in mei_txe_br_reg_write()
154 * mei_txe_aliveness_set - request for aliveness change
163 * Locking: called under "dev->device_lock" lock
170 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_set() local
171 bool do_req = hw->aliveness != req; in mei_txe_aliveness_set()
173 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", in mei_txe_aliveness_set()
174 hw->aliveness, req); in mei_txe_aliveness_set()
176 dev->pg_event = MEI_PG_EVENT_WAIT; in mei_txe_aliveness_set()
177 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); in mei_txe_aliveness_set()
184 * mei_txe_aliveness_req_get - get aliveness requested register value
195 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_req_get() local
198 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); in mei_txe_aliveness_req_get()
203 * mei_txe_aliveness_get - get aliveness response register value
212 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_get() local
215 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); in mei_txe_aliveness_get()
220 * mei_txe_aliveness_poll - waits for aliveness to settle
227 * Return: 0 if the expected value was received, -ETIME otherwise
231 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_poll() local
237 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_poll()
238 if (hw->aliveness == expected) { in mei_txe_aliveness_poll()
239 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_poll()
240 dev_dbg(dev->dev, "aliveness settled after %lld usecs\n", in mei_txe_aliveness_poll()
247 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_poll()
248 dev_err(dev->dev, "aliveness timed out\n"); in mei_txe_aliveness_poll()
249 return -ETIME; in mei_txe_aliveness_poll()
253 * mei_txe_aliveness_wait - waits for aliveness to settle
264 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_aliveness_wait() local
270 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_wait()
271 if (hw->aliveness == expected) in mei_txe_aliveness_wait()
274 mutex_unlock(&dev->device_lock); in mei_txe_aliveness_wait()
275 err = wait_event_timeout(hw->wait_aliveness_resp, in mei_txe_aliveness_wait()
276 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); in mei_txe_aliveness_wait()
277 mutex_lock(&dev->device_lock); in mei_txe_aliveness_wait()
279 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_aliveness_wait()
280 ret = hw->aliveness == expected ? 0 : -ETIME; in mei_txe_aliveness_wait()
283 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", in mei_txe_aliveness_wait()
284 err, hw->aliveness, dev->pg_event); in mei_txe_aliveness_wait()
286 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", in mei_txe_aliveness_wait()
287 jiffies_to_msecs(timeout - err), in mei_txe_aliveness_wait()
288 hw->aliveness, dev->pg_event); in mei_txe_aliveness_wait()
290 dev->pg_event = MEI_PG_EVENT_IDLE; in mei_txe_aliveness_wait()
295 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
310 * mei_txe_pg_in_transition - is device now in pg transition
318 return dev->pg_event == MEI_PG_EVENT_WAIT; in mei_txe_pg_in_transition()
322 * mei_txe_pg_is_enabled - detect if PG is supported by HW
334 * mei_txe_pg_state - translate aliveness register value
343 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_pg_state() local
345 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; in mei_txe_pg_state()
349 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
355 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_input_ready_interrupt_enable() local
358 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); in mei_txe_input_ready_interrupt_enable()
360 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); in mei_txe_input_ready_interrupt_enable()
364 * mei_txe_input_doorbell_set - sets bit 0 in
367 * @hw: the txe hardware structure
369 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) in mei_txe_input_doorbell_set() argument
372 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); in mei_txe_input_doorbell_set()
373 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); in mei_txe_input_doorbell_set()
377 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
379 * @hw: the txe hardware structure
381 static void mei_txe_output_ready_set(struct mei_txe_hw *hw) in mei_txe_output_ready_set() argument
383 mei_txe_br_reg_write(hw, in mei_txe_output_ready_set()
389 * mei_txe_is_input_ready - check if TXE is ready for receiving data
397 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_is_input_ready() local
400 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); in mei_txe_is_input_ready()
405 * mei_txe_intr_clear - clear all interrupts
411 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_clear() local
413 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, in mei_txe_intr_clear()
415 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); in mei_txe_intr_clear()
416 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); in mei_txe_intr_clear()
420 * mei_txe_intr_disable - disable all interrupts
426 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_disable() local
428 mei_txe_br_reg_write(hw, HHIER_REG, 0); in mei_txe_intr_disable()
429 mei_txe_br_reg_write(hw, HIER_REG, 0); in mei_txe_intr_disable()
432 * mei_txe_intr_enable - enable all interrupts
438 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_intr_enable() local
440 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); in mei_txe_intr_enable()
441 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); in mei_txe_intr_enable()
445 * mei_txe_synchronize_irq - wait for pending IRQ handlers
451 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_txe_synchronize_irq()
453 synchronize_irq(pdev->irq); in mei_txe_synchronize_irq()
457 * mei_txe_pending_interrupts - check if there are pending interrupts
470 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_pending_interrupts() local
471 bool ret = (hw->intr_cause & (TXE_INTR_READINESS | in mei_txe_pending_interrupts()
477 dev_dbg(dev->dev, in mei_txe_pending_interrupts()
479 !!(hw->intr_cause & TXE_INTR_IN_READY), in mei_txe_pending_interrupts()
480 !!(hw->intr_cause & TXE_INTR_READINESS), in mei_txe_pending_interrupts()
481 !!(hw->intr_cause & TXE_INTR_ALIVENESS), in mei_txe_pending_interrupts()
482 !!(hw->intr_cause & TXE_INTR_OUT_DB)); in mei_txe_pending_interrupts()
488 * mei_txe_input_payload_write - write a dword to the host buffer
498 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_input_payload_write() local
500 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + in mei_txe_input_payload_write()
505 * mei_txe_out_data_read - read dword from the device buffer
516 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_out_data_read() local
518 return mei_txe_br_reg_read(hw, in mei_txe_out_data_read()
525 * mei_txe_readiness_set_host_rdy - set host readiness bit
531 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_set_host_rdy() local
533 mei_txe_br_reg_write(hw, in mei_txe_readiness_set_host_rdy()
539 * mei_txe_readiness_clear - clear host readiness bit
545 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_clear() local
547 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, in mei_txe_readiness_clear()
551 * mei_txe_readiness_get - Reads and returns
560 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_readiness_get() local
562 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); in mei_txe_readiness_get()
567 * mei_txe_readiness_is_sec_rdy - check readiness
580 * mei_txe_hw_is_ready - check if the hw is ready
594 * mei_txe_host_is_ready - check if the host is ready
602 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_host_is_ready() local
603 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); in mei_txe_host_is_ready()
609 * mei_txe_readiness_wait - wait till readiness settles
613 * Return: 0 on success and -ETIME on timeout
620 mutex_unlock(&dev->device_lock); in mei_txe_readiness_wait()
621 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, in mei_txe_readiness_wait()
623 mutex_lock(&dev->device_lock); in mei_txe_readiness_wait()
624 if (!dev->recvd_hw_ready) { in mei_txe_readiness_wait()
625 dev_err(dev->dev, "wait for readiness failed\n"); in mei_txe_readiness_wait()
626 return -ETIME; in mei_txe_readiness_wait()
629 dev->recvd_hw_ready = false; in mei_txe_readiness_wait()
640 * mei_txe_fw_status - read fw status register from pci config space
651 struct pci_dev *pdev = to_pci_dev(dev->dev); in mei_txe_fw_status()
656 return -EINVAL; in mei_txe_fw_status()
658 fw_status->count = fw_src->count; in mei_txe_fw_status()
659 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { in mei_txe_fw_status()
660 ret = pci_read_config_dword(pdev, fw_src->status[i], in mei_txe_fw_status()
661 &fw_status->status[i]); in mei_txe_fw_status()
662 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", in mei_txe_fw_status()
663 fw_src->status[i], in mei_txe_fw_status()
664 fw_status->status[i]); in mei_txe_fw_status()
673 * mei_txe_hw_config - configure hardware at the start of the devices
678 * once at the device probe time
683 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_config() local
685 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_hw_config()
686 hw->readiness = mei_txe_readiness_get(dev); in mei_txe_hw_config()
688 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", in mei_txe_hw_config()
689 hw->aliveness, hw->readiness); in mei_txe_hw_config()
693 * mei_txe_write - writes a message to device.
697 * @hdr_len: header length in bytes - must multiplication of a slot (4bytes)
701 * Return: 0 if success, < 0 - otherwise.
707 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_write() local
715 return -EINVAL; in mei_txe_write()
717 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr)); in mei_txe_write()
721 return -EMSGSIZE; in mei_txe_write()
723 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) in mei_txe_write()
724 return -EAGAIN; in mei_txe_write()
733 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str); in mei_txe_write()
734 return -EAGAIN; in mei_txe_write()
749 memcpy(®, (const u8 *)data + data_len - rem, rem); in mei_txe_write()
754 hw->slots = 0; in mei_txe_write()
756 /* Set Input-Doorbell */ in mei_txe_write()
757 mei_txe_input_doorbell_set(hw); in mei_txe_write()
763 * mei_txe_hbuf_depth - mimics the me hbuf circular buffer
775 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
783 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hbuf_empty_slots() local
785 return hw->slots; in mei_txe_hbuf_empty_slots()
789 * mei_txe_count_full_read_slots - mimics the me device circular buffer
802 * mei_txe_read_hdr - read message header which is always in 4 first bytes
814 * mei_txe_read - reads a message from the txe device.
820 * Return: -EINVAL on error wrong argument and 0 on success
826 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_read() local
832 return -EINVAL; in mei_txe_read()
837 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", in mei_txe_read()
843 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); in mei_txe_read()
852 mei_txe_output_ready_set(hw); in mei_txe_read()
857 * mei_txe_hw_reset - resets host and fw.
866 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_reset() local
873 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); in mei_txe_hw_reset()
876 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_hw_reset()
884 * Since we might have interrupts disabled - poll for it in mei_txe_hw_reset()
886 if (aliveness_req != hw->aliveness) in mei_txe_hw_reset()
888 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); in mei_txe_hw_reset()
889 return -EIO; in mei_txe_hw_reset()
898 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); in mei_txe_hw_reset()
899 return -EIO; in mei_txe_hw_reset()
912 * mei_txe_hw_start - start the hardware after reset
920 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_hw_start() local
930 dev_err(dev->dev, "waiting for readiness failed\n"); in mei_txe_hw_start()
937 hisr = mei_txe_br_reg_read(hw, HISR_REG); in mei_txe_hw_start()
939 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); in mei_txe_hw_start()
942 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); in mei_txe_hw_start()
946 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); in mei_txe_hw_start()
950 pm_runtime_set_active(dev->dev); in mei_txe_hw_start()
959 mei_txe_output_ready_set(hw); in mei_txe_hw_start()
969 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
979 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_check_and_ack_intrs() local
987 hhisr = mei_txe_br_reg_read(hw, HHISR_REG); in mei_txe_check_and_ack_intrs()
992 hisr = mei_txe_br_reg_read(hw, HISR_REG); in mei_txe_check_and_ack_intrs()
996 ipc_isr = mei_txe_sec_reg_read_silent(hw, in mei_txe_check_and_ack_intrs()
1009 hw->intr_cause |= hisr & HISR_INT_STS_MSK; in mei_txe_check_and_ack_intrs()
1011 hw->intr_cause |= TXE_INTR_IN_READY; in mei_txe_check_and_ack_intrs()
1017 mei_txe_sec_reg_write_silent(hw, in mei_txe_check_and_ack_intrs()
1019 mei_txe_br_reg_write(hw, HISR_REG, hisr); in mei_txe_check_and_ack_intrs()
1020 mei_txe_br_reg_write(hw, HHISR_REG, hhisr); in mei_txe_check_and_ack_intrs()
1028 * mei_txe_irq_quick_handler - The ISR of the MEI device
1047 * mei_txe_irq_thread_handler - txe interrupt thread
1057 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_irq_thread_handler() local
1062 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", in mei_txe_irq_thread_handler()
1063 mei_txe_br_reg_read(hw, HHISR_REG), in mei_txe_irq_thread_handler()
1064 mei_txe_br_reg_read(hw, HISR_REG), in mei_txe_irq_thread_handler()
1065 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); in mei_txe_irq_thread_handler()
1069 mutex_lock(&dev->device_lock); in mei_txe_irq_thread_handler()
1072 if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) in mei_txe_irq_thread_handler()
1078 hw->aliveness = mei_txe_aliveness_get(dev); in mei_txe_irq_thread_handler()
1079 hw->readiness = mei_txe_readiness_get(dev); in mei_txe_irq_thread_handler()
1085 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1086 dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); in mei_txe_irq_thread_handler()
1089 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { in mei_txe_irq_thread_handler()
1090 dev_dbg(dev->dev, "we need to start the dev.\n"); in mei_txe_irq_thread_handler()
1091 dev->recvd_hw_ready = true; in mei_txe_irq_thread_handler()
1093 dev->recvd_hw_ready = false; in mei_txe_irq_thread_handler()
1094 if (dev->dev_state != MEI_DEV_RESETTING) { in mei_txe_irq_thread_handler()
1096 dev_warn(dev->dev, "FW not ready: resetting.\n"); in mei_txe_irq_thread_handler()
1097 schedule_work(&dev->reset_work); in mei_txe_irq_thread_handler()
1102 wake_up(&dev->wait_hw_ready); in mei_txe_irq_thread_handler()
1111 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1113 dev_dbg(dev->dev, in mei_txe_irq_thread_handler()
1114 "Aliveness Interrupt: Status: %d\n", hw->aliveness); in mei_txe_irq_thread_handler()
1115 dev->pg_event = MEI_PG_EVENT_RECEIVED; in mei_txe_irq_thread_handler()
1116 if (waitqueue_active(&hw->wait_aliveness_resp)) in mei_txe_irq_thread_handler()
1117 wake_up(&hw->wait_aliveness_resp); in mei_txe_irq_thread_handler()
1125 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1129 (dev->dev_state != MEI_DEV_RESETTING && in mei_txe_irq_thread_handler()
1130 dev->dev_state != MEI_DEV_POWER_DOWN)) { in mei_txe_irq_thread_handler()
1131 dev_err(dev->dev, in mei_txe_irq_thread_handler()
1134 schedule_work(&dev->reset_work); in mei_txe_irq_thread_handler()
1139 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { in mei_txe_irq_thread_handler()
1140 dev->hbuf_is_ready = true; in mei_txe_irq_thread_handler()
1141 hw->slots = TXE_HBUF_DEPTH; in mei_txe_irq_thread_handler()
1144 if (hw->aliveness && dev->hbuf_is_ready) { in mei_txe_irq_thread_handler()
1146 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_txe_irq_thread_handler()
1148 if (rets && rets != -EMSGSIZE) in mei_txe_irq_thread_handler()
1149 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", in mei_txe_irq_thread_handler()
1151 dev->hbuf_is_ready = mei_hbuf_is_ready(dev); in mei_txe_irq_thread_handler()
1157 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); in mei_txe_irq_thread_handler()
1159 mutex_unlock(&dev->device_lock); in mei_txe_irq_thread_handler()
1199 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1208 struct mei_txe_hw *hw; in mei_txe_dev_init() local
1210 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) + in mei_txe_dev_init()
1215 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); in mei_txe_dev_init()
1217 hw = to_txe_hw(dev); in mei_txe_dev_init()
1219 init_waitqueue_head(&hw->wait_aliveness_resp); in mei_txe_dev_init()
1225 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1235 struct mei_txe_hw *hw = to_txe_hw(dev); in mei_txe_setup_satt2() local
1243 return -EINVAL; in mei_txe_setup_satt2()
1247 return -EINVAL; in mei_txe_setup_satt2()
1251 return -EINVAL; in mei_txe_setup_satt2()
1255 return -EINVAL; in mei_txe_setup_satt2()
1260 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); in mei_txe_setup_satt2()
1261 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); in mei_txe_setup_satt2()
1262 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); in mei_txe_setup_satt2()
1263 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", in mei_txe_setup_satt2()