Lines Matching +full:ciu +full:- +full:sample
15 #include <linux/mmc/slot-gpio.h>
20 #include "dw_mmc-pltfm.h"
33 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
38 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
48 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
50 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
51 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
52 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
54 cclkin = ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
56 ret = clk_set_rate(host->ciu_clk, cclkin); in dw_mci_rk3288_set_ios()
58 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); in dw_mci_rk3288_set_ios()
60 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
61 if (bus_hz != host->bus_hz) { in dw_mci_rk3288_set_ios()
62 host->bus_hz = bus_hz; in dw_mci_rk3288_set_ios()
64 host->current_speed = 0; in dw_mci_rk3288_set_ios()
68 if (!IS_ERR(priv->sample_clk)) in dw_mci_rk3288_set_ios()
69 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_set_ios()
97 if (!IS_ERR(priv->drv_clk)) { in dw_mci_rk3288_set_ios()
108 switch (ios->timing) { in dw_mci_rk3288_set_ios()
115 if (ios->bus_width == MMC_BUS_WIDTH_8) in dw_mci_rk3288_set_ios()
132 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
141 struct dw_mci *host = slot->host; in dw_mci_rk3288_execute_tuning()
142 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_execute_tuning()
143 struct mmc_host *mmc = slot->mmc; in dw_mci_rk3288_execute_tuning()
153 int longest_range_len = -1; in dw_mci_rk3288_execute_tuning()
154 int longest_range = -1; in dw_mci_rk3288_execute_tuning()
157 if (IS_ERR(priv->sample_clk)) { in dw_mci_rk3288_execute_tuning()
158 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); in dw_mci_rk3288_execute_tuning()
159 return -EIO; in dw_mci_rk3288_execute_tuning()
162 ranges = kmalloc_array(priv->num_phases / 2 + 1, in dw_mci_rk3288_execute_tuning()
165 return -ENOMEM; in dw_mci_rk3288_execute_tuning()
168 for (i = 0; i < priv->num_phases; ) { in dw_mci_rk3288_execute_tuning()
169 clk_set_phase(priv->sample_clk, in dw_mci_rk3288_execute_tuning()
170 TUNING_ITERATION_TO_PHASE(i, priv->num_phases)); in dw_mci_rk3288_execute_tuning()
179 ranges[range_count-1].start = i; in dw_mci_rk3288_execute_tuning()
182 ranges[range_count-1].end = i; in dw_mci_rk3288_execute_tuning()
184 } else if (i == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
193 i += DIV_ROUND_UP(20 * priv->num_phases, 360); in dw_mci_rk3288_execute_tuning()
196 if (i >= priv->num_phases) in dw_mci_rk3288_execute_tuning()
197 i = priv->num_phases - 1; in dw_mci_rk3288_execute_tuning()
204 dev_warn(host->dev, "All phases bad!"); in dw_mci_rk3288_execute_tuning()
205 ret = -EIO; in dw_mci_rk3288_execute_tuning()
211 ranges[0].start = ranges[range_count-1].start; in dw_mci_rk3288_execute_tuning()
212 range_count--; in dw_mci_rk3288_execute_tuning()
215 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { in dw_mci_rk3288_execute_tuning()
216 clk_set_phase(priv->sample_clk, priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
217 dev_info(host->dev, "All phases work, using default phase %d.", in dw_mci_rk3288_execute_tuning()
218 priv->default_sample_phase); in dw_mci_rk3288_execute_tuning()
224 int len = (ranges[i].end - ranges[i].start + 1); in dw_mci_rk3288_execute_tuning()
227 len += priv->num_phases; in dw_mci_rk3288_execute_tuning()
234 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
236 priv->num_phases), in dw_mci_rk3288_execute_tuning()
238 priv->num_phases), in dw_mci_rk3288_execute_tuning()
243 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", in dw_mci_rk3288_execute_tuning()
245 priv->num_phases), in dw_mci_rk3288_execute_tuning()
247 priv->num_phases), in dw_mci_rk3288_execute_tuning()
252 middle_phase %= priv->num_phases; in dw_mci_rk3288_execute_tuning()
253 dev_info(host->dev, "Successfully tuned phase to %d\n", in dw_mci_rk3288_execute_tuning()
254 TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases)); in dw_mci_rk3288_execute_tuning()
256 clk_set_phase(priv->sample_clk, in dw_mci_rk3288_execute_tuning()
258 priv->num_phases)); in dw_mci_rk3288_execute_tuning()
267 struct device_node *np = host->dev->of_node; in dw_mci_rk3288_parse_dt()
270 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); in dw_mci_rk3288_parse_dt()
272 return -ENOMEM; in dw_mci_rk3288_parse_dt()
274 if (of_property_read_u32(np, "rockchip,desired-num-phases", in dw_mci_rk3288_parse_dt()
275 &priv->num_phases)) in dw_mci_rk3288_parse_dt()
276 priv->num_phases = 360; in dw_mci_rk3288_parse_dt()
278 if (of_property_read_u32(np, "rockchip,default-sample-phase", in dw_mci_rk3288_parse_dt()
279 &priv->default_sample_phase)) in dw_mci_rk3288_parse_dt()
280 priv->default_sample_phase = 0; in dw_mci_rk3288_parse_dt()
282 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); in dw_mci_rk3288_parse_dt()
283 if (IS_ERR(priv->drv_clk)) in dw_mci_rk3288_parse_dt()
284 dev_dbg(host->dev, "ciu-drive not available\n"); in dw_mci_rk3288_parse_dt()
286 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); in dw_mci_rk3288_parse_dt()
287 if (IS_ERR(priv->sample_clk)) in dw_mci_rk3288_parse_dt()
288 dev_dbg(host->dev, "ciu-sample not available\n"); in dw_mci_rk3288_parse_dt()
290 host->priv = priv; in dw_mci_rk3288_parse_dt()
298 host->sdio_id0 = 8; in dw_mci_rockchip_init()
300 if (of_device_is_compatible(host->dev->of_node, in dw_mci_rockchip_init()
301 "rockchip,rk3288-dw-mshc")) in dw_mci_rockchip_init()
302 host->bus_hz /= RK3288_CLKGEN_DIV; in dw_mci_rockchip_init()
329 { .compatible = "rockchip,rk2928-dw-mshc",
331 { .compatible = "rockchip,rk3288-dw-mshc",
343 if (!pdev->dev.of_node) in dw_mci_rockchip_probe()
344 return -ENODEV; in dw_mci_rockchip_probe()
346 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); in dw_mci_rockchip_probe()
347 drv_data = match->data; in dw_mci_rockchip_probe()
349 pm_runtime_get_noresume(&pdev->dev); in dw_mci_rockchip_probe()
350 pm_runtime_set_active(&pdev->dev); in dw_mci_rockchip_probe()
351 pm_runtime_enable(&pdev->dev); in dw_mci_rockchip_probe()
352 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in dw_mci_rockchip_probe()
353 pm_runtime_use_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
357 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_probe()
358 pm_runtime_set_suspended(&pdev->dev); in dw_mci_rockchip_probe()
359 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_probe()
363 pm_runtime_put_autosuspend(&pdev->dev); in dw_mci_rockchip_probe()
370 pm_runtime_get_sync(&pdev->dev); in dw_mci_rockchip_remove()
371 pm_runtime_disable(&pdev->dev); in dw_mci_rockchip_remove()
372 pm_runtime_put_noidle(&pdev->dev); in dw_mci_rockchip_remove()
397 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
398 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");