24 #include "sdhci-pltfm.h"
26 /* HRS - Host Register Set (specific to Cadence) */
46 /* SRS - Slot Register Set (SDHCI-compatible) */
64  * The tuned val register is 6 bit-wide, but not the whole of the range is
65  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
88 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
89 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
90 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
91 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
92 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
93 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
94 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
95 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
96 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
97 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
98 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
104 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;  in sdhci_cdns_write_phy_reg()
140 	struct sdhci_cdns_phy_param *p = priv->phy_params;  in sdhci_cdns_phy_param_parse()
150 		p->addr = sdhci_cdns_phy_cfgs[i].addr;  in sdhci_cdns_phy_param_parse()
151 		p->data = val;  in sdhci_cdns_phy_param_parse()
160 	for (i = 0; i < priv->nr_phy_params; i++) {  in sdhci_cdns_phy_init()
161 		ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,  in sdhci_cdns_phy_init()
162 					       priv->phy_params[i].data);  in sdhci_cdns_phy_init()
183 	return host->max_clk;  in sdhci_cdns_get_timeout_clock()
191 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_emmc_mode()
194 	writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_set_emmc_mode()
201 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);  in sdhci_cdns_get_emmc_mode()
222 		if (priv->enhanced_strobe)  in sdhci_cdns_set_uhs_signaling()
234 	/* For SD, fall back to the default handler */  in sdhci_cdns_set_uhs_signaling()
254 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;  in sdhci_cdns_set_tune_val()
259 		return -EINVAL;  in sdhci_cdns_set_tune_val()
267 	 * The IP6116 SD/eMMC PHY design has a timing issue on receive data  in sdhci_cdns_set_tune_val()
294 	 * this controller.  Fall back to the standard method for SD timing.  in sdhci_cdns_execute_tuning()
296 	if (host->timing != MMC_TIMING_MMC_HS200)  in sdhci_cdns_execute_tuning()
300 		return -EINVAL;  in sdhci_cdns_execute_tuning()
304 		    mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */  in sdhci_cdns_execute_tuning()
316 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");  in sdhci_cdns_execute_tuning()
317 		return -EIO;  in sdhci_cdns_execute_tuning()
320 	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);  in sdhci_cdns_execute_tuning()
330 	priv->enhanced_strobe = ios->enhanced_strobe;  in sdhci_cdns_hs400_enhanced_strobe()
334 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)  in sdhci_cdns_hs400_enhanced_strobe()
338 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)  in sdhci_cdns_hs400_enhanced_strobe()
352 	struct device *dev = &pdev->dev;  in sdhci_cdns_probe()
362 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);  in sdhci_cdns_probe()
363 	priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params;  in sdhci_cdns_probe()
371 	pltfm_host->clk = clk;  in sdhci_cdns_probe()
374 	priv->nr_phy_params = nr_phy_params;  in sdhci_cdns_probe()
375 	priv->hrs_addr = host->ioaddr;  in sdhci_cdns_probe()
376 	priv->enhanced_strobe = false;  in sdhci_cdns_probe()
377 	host->ioaddr += SDHCI_CDNS_SRS_BASE;  in sdhci_cdns_probe()
378 	host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;  in sdhci_cdns_probe()
379 	host->mmc_host_ops.hs400_enhanced_strobe =  in sdhci_cdns_probe()
384 	ret = mmc_of_parse(host->mmc);  in sdhci_cdns_probe()
388 	sdhci_cdns_phy_param_parse(dev->of_node, priv);  in sdhci_cdns_probe()
415 	ret = clk_prepare_enable(pltfm_host->clk);  in sdhci_cdns_resume()
430 	clk_disable_unprepare(pltfm_host->clk);  in sdhci_cdns_resume()
441 	{ .compatible = "socionext,uniphier-sd4hc" },
449 		.name = "sdhci-cdns",
459 MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");