Lines Matching full:esdhc
3 * Freescale eSDHC i.MX controller driver for the platform bus.
26 #include <linux/platform_data/mmc-esdhc-imx.h>
29 #include "sdhci-esdhc.h"
101 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
102 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
103 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
104 * Define this macro DMA error INT for fsl eSDHC
121 * The flag tells that the ESDHC controller is an USDHC block that is
210 .name = "sdhci-esdhc-imx25",
213 .name = "sdhci-esdhc-imx35",
216 .name = "sdhci-esdhc-imx51",
225 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
226 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
227 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
228 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
286 /* In FSL esdhc IC module, only bit20 is used to indicate the in esdhc_readl_le()
287 * ADMA2 capability of esdhc, but this bit is messed up on in esdhc_readl_le()
364 * card interrupt. This is an eSDHC controller problem in esdhc_writel_le()
366 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
649 * The esdhc has a design violation to SDHC spec which in esdhc_writeb_le()
651 * detection circuit. But esdhc clears its SYSCTL in esdhc_writeb_le()
673 * The eSDHC DAT line software reset clears at least the in esdhc_writeb_le()
1485 .name = "sdhci-esdhc-imx",
1496 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");