Lines Matching +full:imx7d +full:- +full:usdhc
1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
21 #include <linux/mmc/slot-gpio.h>
26 #include <linux/platform_data/mmc-esdhc-imx.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
69 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
111 * open ended multi-blk IO. Otherwise the TC INT wouldn't
121 * The flag tells that the ESDHC controller is an USDHC block that is
133 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
210 .name = "sdhci-esdhc-imx25",
213 .name = "sdhci-esdhc-imx35",
216 .name = "sdhci-esdhc-imx51",
225 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
226 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
227 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
228 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
229 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
230 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
231 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
232 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
239 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
244 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
249 return data->socdata == &usdhc_imx6q_data; in is_imx6q_usdhc()
254 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
259 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
269 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
275 /* move dat[0-3] bits */ in esdhc_readl_le()
282 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
283 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
301 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
302 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
310 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in esdhc_readl_le()
317 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || in esdhc_readl_le()
318 IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
341 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
344 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
346 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
366 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
368 * re-sample it by the following steps. in esdhc_writel_le()
370 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
372 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
374 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
383 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
387 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
389 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
391 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
396 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
397 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
401 writel(val, host->ioaddr + reg); in esdhc_writel_le()
415 * The usdhc register returns a wrong host version. in esdhc_readw_le()
423 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
428 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
429 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
430 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
432 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
447 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
455 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
461 return readw(host->ioaddr + reg); in esdhc_readw_le()
472 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
477 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
480 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
485 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
486 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_writew_le()
487 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
495 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
496 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
497 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
498 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
515 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
516 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
520 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
521 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
522 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
523 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
525 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
527 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
532 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
539 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
545 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
554 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
560 imx_data->scratchpad = val; in esdhc_writew_le()
564 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
567 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
568 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
569 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
573 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
575 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
576 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
592 val = readl(host->ioaddr + reg); in esdhc_readb_le()
601 return readb(host->ioaddr + reg); in esdhc_readb_le()
641 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
659 * The reset on usdhc fails to clear MIX_CTRL register. in esdhc_writeb_le()
666 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
668 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
669 imx_data->is_ddr = 0; in esdhc_writeb_le()
687 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
694 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
702 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
703 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
709 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
711 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
715 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
725 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
726 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
727 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
728 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
745 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
746 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
747 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
750 div--; in esdhc_pltfm_set_clock()
759 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
761 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
771 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
773 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
775 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
777 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
783 return -ENOSYS; in esdhc_pltfm_get_ro()
813 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
816 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
817 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
818 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
820 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
827 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
830 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
841 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
850 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
851 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
860 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
863 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
876 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
878 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
879 IS_ERR(imx_data->pins_default) || in esdhc_change_pinstate()
880 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
881 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
882 return -EINVAL; in esdhc_change_pinstate()
887 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
892 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
896 pinctrl = imx_data->pins_default; in esdhc_change_pinstate()
899 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
917 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { in esdhc_set_strobe_dll()
919 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
921 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
925 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
928 * for the uSDHC loopback read clock in esdhc_set_strobe_dll()
932 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
935 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); in esdhc_set_strobe_dll()
937 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
940 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
953 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
954 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
957 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
958 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
959 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
960 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
962 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
972 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
975 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
977 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
986 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
991 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
992 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
993 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
995 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1000 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1005 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1006 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1008 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1024 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1025 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1033 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ in esdhc_get_max_timeout_count()
1085 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1089 * to zero if this usdhc is chosen to boot system. Change in sdhci_esdhc_imx_hwinit()
1098 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1100 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1106 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1107 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1110 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1112 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1113 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1116 if (imx_data->boarddata.tuning_start_tap) { in sdhci_esdhc_imx_hwinit()
1118 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1121 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1123 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1126 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1137 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1138 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1141 if (of_get_property(np, "fsl,wp-controller", NULL)) in sdhci_esdhc_imx_probe_dt()
1142 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1144 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); in sdhci_esdhc_imx_probe_dt()
1145 if (gpio_is_valid(boarddata->wp_gpio)) in sdhci_esdhc_imx_probe_dt()
1146 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1148 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1149 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1150 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1152 if (of_find_property(np, "no-1-8-v", NULL)) in sdhci_esdhc_imx_probe_dt()
1153 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1155 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1156 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1158 mmc_of_parse_voltage(np, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1160 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pins_default)) { in sdhci_esdhc_imx_probe_dt()
1161 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1163 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1168 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1172 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1173 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1183 return -ENODEV; in sdhci_esdhc_imx_probe_dt()
1191 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_nondt()
1194 if (!host->mmc->parent->platform_data) { in sdhci_esdhc_imx_probe_nondt()
1195 dev_err(mmc_dev(host->mmc), "no board data!\n"); in sdhci_esdhc_imx_probe_nondt()
1196 return -EINVAL; in sdhci_esdhc_imx_probe_nondt()
1199 imx_data->boarddata = *((struct esdhc_platform_data *) in sdhci_esdhc_imx_probe_nondt()
1200 host->mmc->parent->platform_data); in sdhci_esdhc_imx_probe_nondt()
1202 if (boarddata->wp_type == ESDHC_WP_GPIO) { in sdhci_esdhc_imx_probe_nondt()
1203 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); in sdhci_esdhc_imx_probe_nondt()
1205 dev_err(mmc_dev(host->mmc), in sdhci_esdhc_imx_probe_nondt()
1206 "failed to request write-protect gpio!\n"); in sdhci_esdhc_imx_probe_nondt()
1209 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; in sdhci_esdhc_imx_probe_nondt()
1213 switch (boarddata->cd_type) { in sdhci_esdhc_imx_probe_nondt()
1215 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); in sdhci_esdhc_imx_probe_nondt()
1217 dev_err(mmc_dev(host->mmc), in sdhci_esdhc_imx_probe_nondt()
1218 "failed to request card-detect gpio!\n"); in sdhci_esdhc_imx_probe_nondt()
1225 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_nondt()
1229 host->mmc->caps |= MMC_CAP_NONREMOVABLE; in sdhci_esdhc_imx_probe_nondt()
1236 switch (boarddata->max_bus_width) { in sdhci_esdhc_imx_probe_nondt()
1238 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1241 host->mmc->caps |= MMC_CAP_4_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1245 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; in sdhci_esdhc_imx_probe_nondt()
1255 of_match_device(imx_esdhc_dt_ids, &pdev->dev); in sdhci_esdhc_imx_probe()
1270 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) in sdhci_esdhc_imx_probe()
1271 pdev->id_entry->driver_data; in sdhci_esdhc_imx_probe()
1273 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1274 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1275 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1279 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1280 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1281 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1285 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1286 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1287 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1291 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1292 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1293 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1296 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1299 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1303 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1304 if (IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe()
1305 err = PTR_ERR(imx_data->pinctrl); in sdhci_esdhc_imx_probe()
1309 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe()
1311 if (IS_ERR(imx_data->pins_default)) in sdhci_esdhc_imx_probe()
1312 dev_warn(mmc_dev(host->mmc), "could not get default state\n"); in sdhci_esdhc_imx_probe()
1315 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1316 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1317 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1318 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1321 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1322 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1323 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1326 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1330 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1331 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1333 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1334 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; in sdhci_esdhc_imx_probe()
1349 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1350 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1351 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1352 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1353 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1358 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1360 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1362 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1373 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1375 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1376 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1377 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1381 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1382 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1383 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1395 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1396 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1405 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1424 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1425 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1428 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1430 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1431 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1433 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1445 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1450 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1453 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1456 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1467 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1470 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1472 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1485 .name = "sdhci-esdhc-imx",