2  * Support for SDHCI on STMicroelectronics SoCs
8  * Based on sdhci-cns3xxx.c
27 #include "sdhci-pltfm.h"
40 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
68 #define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
81 #define ST_MMC_CCONFIG_DDR50	BIT(8)
87 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
97 #define ST_TOP_MMC_DLY_FIX_OFF(x)	(x - 0x8)
106 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE	BIT(8)
111 /* register to provide the phase-shift value for DLL */
128  * DLL procedure has finished before switching to ultra-speed modes.
145  * @host: sdhci host
148  * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
149  * or eMMC4.3.  This has to be done before registering the sdhci host.
154 	struct mmc_host *mhost = host->mmc;  in st_mmcss_cconfig()
157 	if (!of_device_is_compatible(np, "st,sdhci-stih407"))  in st_mmcss_cconfig()
166 			host->ioaddr + ST_MMC_CCONFIG_REG_1);  in st_mmcss_cconfig()
168 	/* Set clock frequency, default to 50MHz if max-frequency is not  in st_mmcss_cconfig()
171 	switch (mhost->f_max) {  in st_mmcss_cconfig()
173 		clk_set_rate(pltfm_host->clk, mhost->f_max);  in st_mmcss_cconfig()
177 		clk_set_rate(pltfm_host->clk, mhost->f_max);  in st_mmcss_cconfig()
181 		clk_set_rate(pltfm_host->clk, 50000000);  in st_mmcss_cconfig()
185 	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);  in st_mmcss_cconfig()
192 				host->ioaddr + ST_MMC_GP_OUTPUT);  in st_mmcss_cconfig()
194 	if (mhost->caps & MMC_CAP_UHS_SDR50) {  in st_mmcss_cconfig()
204 	if (mhost->caps & MMC_CAP_UHS_SDR104) {  in st_mmcss_cconfig()
215 	if (mhost->caps & MMC_CAP_UHS_DDR50)  in st_mmcss_cconfig()
218 	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);  in st_mmcss_cconfig()
219 	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);  in st_mmcss_cconfig()
220 	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);  in st_mmcss_cconfig()
248 	return -EBUSY;  in st_mmcss_lock_dll()
257 	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {  in sdhci_st_set_dll_for_clock()
258 		st_mmcss_set_dll(pdata->top_ioaddr);  in sdhci_st_set_dll_for_clock()
259 		ret = st_mmcss_lock_dll(host->ioaddr);  in sdhci_st_set_dll_for_clock()
277 	 * Set V18_EN -- UHS modes do not work without this.  in sdhci_st_set_uhs_signaling()
282 		st_mmcss_set_static_delay(pdata->top_ioaddr);  in sdhci_st_set_uhs_signaling()
286 		st_mmcss_set_static_delay(pdata->top_ioaddr);  in sdhci_st_set_uhs_signaling()
290 		st_mmcss_set_static_delay(pdata->top_ioaddr);  in sdhci_st_set_uhs_signaling()
296 		st_mmcss_set_static_delay(pdata->top_ioaddr);  in sdhci_st_set_uhs_signaling()
302 		st_mmcss_set_static_delay(pdata->top_ioaddr);  in sdhci_st_set_uhs_signaling()
308 		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock "  in sdhci_st_set_uhs_signaling()
311 	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);  in sdhci_st_set_uhs_signaling()
322 		ret = readl_relaxed(host->ioaddr + reg);  in sdhci_st_readl()
327 		ret = readl_relaxed(host->ioaddr + reg);  in sdhci_st_readl()
353 	struct device_node *np = pdev->dev.of_node;  in sdhci_st_probe()
363 	clk =  devm_clk_get(&pdev->dev, "mmc");  in sdhci_st_probe()
365 		dev_err(&pdev->dev, "Peripheral clk not found\n");  in sdhci_st_probe()
370 	icnclk = devm_clk_get(&pdev->dev, "icn");  in sdhci_st_probe()
374 	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in sdhci_st_probe()
382 		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");  in sdhci_st_probe()
389 	pdata->rstc = rstc;  in sdhci_st_probe()
391 	ret = mmc_of_parse(host->mmc);  in sdhci_st_probe()
393 		dev_err(&pdev->dev, "Failed mmc_of_parse\n");  in sdhci_st_probe()
399 		dev_err(&pdev->dev, "Failed to prepare clock\n");  in sdhci_st_probe()
405 		dev_err(&pdev->dev, "Failed to prepare icn clock\n");  in sdhci_st_probe()
411 					   "top-mmc-delay");  in sdhci_st_probe()
412 	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);  in sdhci_st_probe()
413 	if (IS_ERR(pdata->top_ioaddr)) {  in sdhci_st_probe()
414 		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");  in sdhci_st_probe()
415 		pdata->top_ioaddr = NULL;  in sdhci_st_probe()
418 	pltfm_host->clk = clk;  in sdhci_st_probe()
419 	pdata->icnclk = icnclk;  in sdhci_st_probe()
428 	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));  in sdhci_st_probe()
430 	dev_info(&pdev->dev, "SDHCI ST Initialised: Host Version: 0x%x Vendor Version 0x%x\n",  in sdhci_st_probe()
455 	struct reset_control *rstc = pdata->rstc;  in sdhci_st_remove()
460 	clk_disable_unprepare(pdata->icnclk);  in sdhci_st_remove()
476 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)  in sdhci_st_suspend()
477 		mmc_retune_needed(host->mmc);  in sdhci_st_suspend()
483 	if (pdata->rstc)  in sdhci_st_suspend()
484 		reset_control_assert(pdata->rstc);  in sdhci_st_suspend()
486 	clk_disable_unprepare(pdata->icnclk);  in sdhci_st_suspend()
487 	clk_disable_unprepare(pltfm_host->clk);  in sdhci_st_suspend()
497 	struct device_node *np = dev->of_node;  in sdhci_st_resume()
500 	ret = clk_prepare_enable(pltfm_host->clk);  in sdhci_st_resume()
504 	ret = clk_prepare_enable(pdata->icnclk);  in sdhci_st_resume()
506 		clk_disable_unprepare(pltfm_host->clk);  in sdhci_st_resume()
510 	if (pdata->rstc)  in sdhci_st_resume()
511 		reset_control_deassert(pdata->rstc);  in sdhci_st_resume()
522 	{ .compatible = "st,sdhci" },
532 		   .name = "sdhci-st",
540 MODULE_DESCRIPTION("SDHCI driver for STMicroelectronics SoCs");
543 MODULE_ALIAS("platform:sdhci-st");