Lines Matching +full:tuning +full:- +full:step
7 * Date: 2016-8-24
19 #include "sdhci-pltfm.h"
20 #include "sdhci-xenon.h"
197 /* Divider for calculating Tuning Step */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; in xenon_alloc_emmc_phy()
217 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; in xenon_alloc_emmc_phy()
223 * eMMC 5.0/5.1 PHY init/re-init.
226 * 2. SDCLK is stopped and re-enabled.
227 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
236 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; in xenon_emmc_phy_init()
238 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
240 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_init()
258 clock = host->clock; in xenon_emmc_phy_init()
268 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
271 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", in xenon_emmc_phy_init()
273 return -ETIMEDOUT; in xenon_emmc_phy_init()
287 struct xenon_emmc_phy_params *params = priv->phy_params; in armada_3700_soc_pad_voltage_set()
289 if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { in armada_3700_soc_pad_voltage_set()
290 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); in armada_3700_soc_pad_voltage_set()
291 } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { in armada_3700_soc_pad_voltage_set()
293 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); in armada_3700_soc_pad_voltage_set()
295 writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); in armada_3700_soc_pad_voltage_set()
309 struct xenon_emmc_phy_params *params = priv->phy_params; in xenon_emmc_phy_set_soc_pad()
311 if (!params->pad_ctrl.reg) in xenon_emmc_phy_set_soc_pad()
314 if (params->pad_ctrl.set_soc_pad) in xenon_emmc_phy_set_soc_pad()
315 params->pad_ctrl.set_soc_pad(host, signal_voltage); in xenon_emmc_phy_set_soc_pad()
320 * DLL should be enabled and stable before HS200/SDR104 tuning,
328 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; in xenon_emmc_phy_enable_dll()
331 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR)) in xenon_emmc_phy_enable_dll()
332 return -EINVAL; in xenon_emmc_phy_enable_dll()
334 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
339 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
353 reg |= phy_regs->dll_update; in xenon_emmc_phy_enable_dll()
354 if (priv->phy_type == EMMC_5_1_PHY) in xenon_emmc_phy_enable_dll()
356 sdhci_writel(host, reg, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
367 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); in xenon_emmc_phy_enable_dll()
368 return -ETIMEDOUT; in xenon_emmc_phy_enable_dll()
376 * Config to eMMC PHY to prepare for tuning.
383 struct xenon_emmc_phy_params *params = priv->phy_params; in xenon_emmc_phy_config_tuning()
387 if (host->clock <= MMC_HIGH_52_MAX_DTR) in xenon_emmc_phy_config_tuning()
388 return -EINVAL; in xenon_emmc_phy_config_tuning()
396 tuning_step = reg / params->tun_step_divider; in xenon_emmc_phy_config_tuning()
398 dev_warn(mmc_dev(host->mmc), in xenon_emmc_phy_config_tuning()
404 /* Set TUNING_STEP for later tuning */ in xenon_emmc_phy_config_tuning()
408 reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); in xenon_emmc_phy_config_tuning()
428 if (priv->phy_type == EMMC_5_0_PHY) { in xenon_emmc_phy_disable_strobe()
446 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) in xenon_emmc_phy_strobe_delay_adj()
449 if (host->clock <= MMC_HIGH_52_MAX_DTR) in xenon_emmc_phy_strobe_delay_adj()
452 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); in xenon_emmc_phy_strobe_delay_adj()
466 if (host->mmc->ios.enhanced_strobe) in xenon_emmc_phy_strobe_delay_adj()
471 if (priv->phy_type == EMMC_5_0_PHY) { in xenon_emmc_phy_strobe_delay_adj()
497 struct xenon_emmc_phy_params *params = priv->phy_params; in xenon_emmc_phy_slow_mode()
498 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; in xenon_emmc_phy_slow_mode()
502 if (host->clock > MMC_HIGH_52_MAX_DTR) in xenon_emmc_phy_slow_mode()
505 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_slow_mode()
515 if (params->slow_mode) { in xenon_emmc_phy_slow_mode()
527 if ((priv->init_card_type == MMC_TYPE_SDIO) || in xenon_emmc_phy_slow_mode()
528 params->slow_mode) { in xenon_emmc_phy_slow_mode()
539 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_slow_mode()
544 * Set-up eMMC 5.0/5.1 PHY.
553 struct xenon_emmc_phy_params *params = priv->phy_params; in xenon_emmc_phy_set()
554 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; in xenon_emmc_phy_set()
556 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n"); in xenon_emmc_phy_set()
559 reg = sdhci_readl(host, phy_regs->pad_ctrl); in xenon_emmc_phy_set()
564 sdhci_writel(host, reg, phy_regs->pad_ctrl); in xenon_emmc_phy_set()
567 if (priv->phy_type == EMMC_5_0_PHY) { in xenon_emmc_phy_set()
588 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_set()
589 if (priv->init_card_type == MMC_TYPE_SDIO) in xenon_emmc_phy_set()
593 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_set()
601 * Define them both in sdhci-xenon-emmc-phy.h. in xenon_emmc_phy_set()
603 reg = sdhci_readl(host, phy_regs->pad_ctrl2); in xenon_emmc_phy_set()
605 reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); in xenon_emmc_phy_set()
606 sdhci_writel(host, reg, phy_regs->pad_ctrl2); in xenon_emmc_phy_set()
616 reg = sdhci_readl(host, phy_regs->func_ctrl); in xenon_emmc_phy_set()
633 sdhci_writel(host, reg, phy_regs->func_ctrl); in xenon_emmc_phy_set()
642 sdhci_writel(host, phy_regs->logic_timing_val, in xenon_emmc_phy_set()
643 phy_regs->logic_timing_adj); in xenon_emmc_phy_set()
650 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); in xenon_emmc_phy_set()
661 if (of_device_is_compatible(np, "marvell,armada-3700-sdhci")) in get_dt_pad_ctrl_data()
662 params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; in get_dt_pad_ctrl_data()
667 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n", in get_dt_pad_ctrl_data()
668 np->name); in get_dt_pad_ctrl_data()
669 return -EINVAL; in get_dt_pad_ctrl_data()
672 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), in get_dt_pad_ctrl_data()
674 if (IS_ERR(params->pad_ctrl.reg)) in get_dt_pad_ctrl_data()
675 return PTR_ERR(params->pad_ctrl.reg); in get_dt_pad_ctrl_data()
677 ret = of_property_read_string(np, "marvell,pad-type", &name); in get_dt_pad_ctrl_data()
679 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); in get_dt_pad_ctrl_data()
683 params->pad_ctrl.pad_type = SOC_PAD_SD; in get_dt_pad_ctrl_data()
684 } else if (!strcmp(name, "fixed-1-8v")) { in get_dt_pad_ctrl_data()
685 params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; in get_dt_pad_ctrl_data()
687 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", in get_dt_pad_ctrl_data()
689 return -EINVAL; in get_dt_pad_ctrl_data()
701 params->slow_mode = false; in xenon_emmc_phy_parse_param_dt()
702 if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode")) in xenon_emmc_phy_parse_param_dt()
703 params->slow_mode = true; in xenon_emmc_phy_parse_param_dt()
705 params->znr = XENON_ZNR_DEF_VALUE; in xenon_emmc_phy_parse_param_dt()
706 if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value)) in xenon_emmc_phy_parse_param_dt()
707 params->znr = value & XENON_ZNR_MASK; in xenon_emmc_phy_parse_param_dt()
709 params->zpr = XENON_ZPR_DEF_VALUE; in xenon_emmc_phy_parse_param_dt()
710 if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value)) in xenon_emmc_phy_parse_param_dt()
711 params->zpr = value & XENON_ZPR_MASK; in xenon_emmc_phy_parse_param_dt()
713 params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES; in xenon_emmc_phy_parse_param_dt()
714 if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun", in xenon_emmc_phy_parse_param_dt()
716 params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK; in xenon_emmc_phy_parse_param_dt()
718 params->tun_step_divider = XENON_TUNING_STEP_DIVIDER; in xenon_emmc_phy_parse_param_dt()
719 if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider", in xenon_emmc_phy_parse_param_dt()
721 params->tun_step_divider = value & 0xFF; in xenon_emmc_phy_parse_param_dt()
736 * HS200/SDR104 set tuning config to prepare for tuning.
742 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ)) in xenon_hs_delay_adj()
743 return -EINVAL; in xenon_hs_delay_adj()
745 switch (host->timing) { in xenon_hs_delay_adj()
765 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n"); in xenon_hs_delay_adj()
785 if (!host->clock) { in xenon_phy_adj()
786 priv->clock = 0; in xenon_phy_adj()
795 if ((host->clock == priv->clock) && in xenon_phy_adj()
796 (ios->bus_width == priv->bus_width) && in xenon_phy_adj()
797 (ios->timing == priv->timing)) in xenon_phy_adj()
800 xenon_emmc_phy_set(host, ios->timing); in xenon_phy_adj()
803 priv->bus_width = ios->bus_width; in xenon_phy_adj()
805 priv->timing = ios->timing; in xenon_phy_adj()
806 priv->clock = host->clock; in xenon_phy_adj()
809 if (ios->timing == MMC_TIMING_LEGACY) in xenon_phy_adj()
812 if (host->clock > XENON_DEFAULT_SDCLK_FREQ) in xenon_phy_adj()
824 priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name); in xenon_add_phy()
825 if (priv->phy_type < 0) { in xenon_add_phy()
826 dev_err(mmc_dev(host->mmc), in xenon_add_phy()
829 priv->phy_type = EMMC_5_1_PHY; in xenon_add_phy()
836 return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params); in xenon_add_phy()
843 if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type)) in xenon_phy_parse_dt()