2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
33 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))  argument
161 #define SDHCI_INT_ALL_MASK	((unsigned int)-1)
183 #define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
227 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
241 /* 4C-4F reserved for more max current */
248 /* 55-57 reserved */
253 /* 60-FB reserved */
260 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
290 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
292 /* ADMA2 32-bit DMA descriptor size */
295 /* ADMA2 32-bit descriptor */
304 #define SDHCI_ADMA2_MASK	(SDHCI_ADMA2_ALIGN - 1)
308  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
313 /* ADMA2 64-bit DMA descriptor size */
317  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
362 /* Controller has bad caps bits, but really supports DMA */
370 /* Controller has an unusable DMA engine */
374 /* Controller can only DMA from 32-bit aligned addresses */
376 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
388 /* Controller does not provide transfer-complete interrupt when not busy */
392 /* Controller reports inverted write-protect state */
400 /* Controller cannot do multi-block transfers */
402 /* Controller can only handle 1-bit data transfers */
416 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
420 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
431 /* Controller has a non-standard host control register */
439 /* Controller does not support 64-bit DMA */
443 /* Capability register bit-63 indicates HS400 support */
472 	u64 dma_mask;		/* custom DMA mask */
482 #define SDHCI_USE_SDMA		(1<<0)	/* Host is SDMA capable */
483 #define SDHCI_USE_ADMA		(1<<1)	/* Host is ADMA capable */
484 #define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
491 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
493 #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
494 #define SDHCI_SIGNALING_180	(1<<15)	/* Host is capable of 1.8V signaling */
495 #define SDHCI_SIGNALING_120	(1<<16)	/* Host is capable of 1.2V signaling */
562 	unsigned int		tuning_count;	/* Timer count for re-tuning */
563 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
619 	if (unlikely(host->ops->write_l))  in sdhci_writel()
620 		host->ops->write_l(host, val, reg);  in sdhci_writel()
622 		writel(val, host->ioaddr + reg);  in sdhci_writel()
627 	if (unlikely(host->ops->write_w))  in sdhci_writew()
628 		host->ops->write_w(host, val, reg);  in sdhci_writew()
630 		writew(val, host->ioaddr + reg);  in sdhci_writew()
635 	if (unlikely(host->ops->write_b))  in sdhci_writeb()
636 		host->ops->write_b(host, val, reg);  in sdhci_writeb()
638 		writeb(val, host->ioaddr + reg);  in sdhci_writeb()
643 	if (unlikely(host->ops->read_l))  in sdhci_readl()
644 		return host->ops->read_l(host, reg);  in sdhci_readl()
646 		return readl(host->ioaddr + reg);  in sdhci_readl()
651 	if (unlikely(host->ops->read_w))  in sdhci_readw()
652 		return host->ops->read_w(host, reg);  in sdhci_readw()
654 		return readw(host->ioaddr + reg);  in sdhci_readw()
659 	if (unlikely(host->ops->read_b))  in sdhci_readb()
660 		return host->ops->read_b(host, reg);  in sdhci_readb()
662 		return readb(host->ioaddr + reg);  in sdhci_readb()
669 	writel(val, host->ioaddr + reg);  in sdhci_writel()
674 	writew(val, host->ioaddr + reg);  in sdhci_writew()
679 	writeb(val, host->ioaddr + reg);  in sdhci_writeb()
684 	return readl(host->ioaddr + reg);  in sdhci_readl()
689 	return readw(host->ioaddr + reg);  in sdhci_readw()
694 	return readb(host->ioaddr + reg);  in sdhci_readb()
704 	return host->private;  in sdhci_priv()
724 	return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);  in sdhci_sdio_irq_enabled()