Lines Matching full:q
302 static inline int needs_swap_endian(struct fsl_qspi *q) in needs_swap_endian() argument
304 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN; in needs_swap_endian()
307 static inline int needs_4x_clock(struct fsl_qspi *q) in needs_4x_clock() argument
309 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK; in needs_4x_clock()
312 static inline int needs_fill_txfifo(struct fsl_qspi *q) in needs_fill_txfifo() argument
314 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890; in needs_fill_txfifo()
317 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) in needs_wakeup_wait_mode() argument
319 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618; in needs_wakeup_wait_mode()
328 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) in qspi_writel() argument
330 if (q->big_endian) in qspi_writel()
336 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) in qspi_readl() argument
338 if (q->big_endian) in qspi_readl()
348 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) in fsl_qspi_endian_xchg() argument
350 return needs_swap_endian(q) ? __swab32(a) : a; in fsl_qspi_endian_xchg()
353 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q) in fsl_qspi_unlock_lut() argument
355 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_unlock_lut()
356 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_unlock_lut()
359 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q) in fsl_qspi_lock_lut() argument
361 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_lock_lut()
362 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_lock_lut()
367 struct fsl_qspi *q = dev_id; in fsl_qspi_irq_handler() local
371 reg = qspi_readl(q, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
372 qspi_writel(q, reg, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
375 complete(&q->c); in fsl_qspi_irq_handler()
377 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg); in fsl_qspi_irq_handler()
381 static void fsl_qspi_init_lut(struct fsl_qspi *q) in fsl_qspi_init_lut() argument
383 void __iomem *base = q->iobase; in fsl_qspi_init_lut()
384 int rxfifo = q->devtype_data->rxfifo; in fsl_qspi_init_lut()
388 struct spi_nor *nor = &q->nor[0]; in fsl_qspi_init_lut()
393 fsl_qspi_unlock_lut(q); in fsl_qspi_init_lut()
397 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4); in fsl_qspi_init_lut()
402 qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
404 qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | in fsl_qspi_init_lut()
410 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN), in fsl_qspi_init_lut()
416 qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | in fsl_qspi_init_lut()
419 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), in fsl_qspi_init_lut()
424 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) | in fsl_qspi_init_lut()
431 qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | in fsl_qspi_init_lut()
437 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), in fsl_qspi_init_lut()
442 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) | in fsl_qspi_init_lut()
448 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) | in fsl_qspi_init_lut()
454 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) | in fsl_qspi_init_lut()
460 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI), in fsl_qspi_init_lut()
465 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B), in fsl_qspi_init_lut()
470 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR), in fsl_qspi_init_lut()
473 fsl_qspi_lock_lut(q); in fsl_qspi_init_lut()
477 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) in fsl_qspi_get_seqid() argument
506 if (cmd == q->nor[0].erase_opcode) in fsl_qspi_get_seqid()
508 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd); in fsl_qspi_get_seqid()
515 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len) in fsl_qspi_runcmd() argument
517 void __iomem *base = q->iobase; in fsl_qspi_runcmd()
522 init_completion(&q->c); in fsl_qspi_runcmd()
523 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n", in fsl_qspi_runcmd()
524 q->chip_base_addr, addr, len, cmd); in fsl_qspi_runcmd()
527 reg = qspi_readl(q, base + QUADSPI_MCR); in fsl_qspi_runcmd()
529 qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr, in fsl_qspi_runcmd()
531 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, in fsl_qspi_runcmd()
533 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); in fsl_qspi_runcmd()
536 reg2 = qspi_readl(q, base + QUADSPI_SR); in fsl_qspi_runcmd()
539 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2); in fsl_qspi_runcmd()
546 seqid = fsl_qspi_get_seqid(q, cmd); in fsl_qspi_runcmd()
550 qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, in fsl_qspi_runcmd()
554 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) { in fsl_qspi_runcmd()
555 dev_err(q->dev, in fsl_qspi_runcmd()
557 cmd, addr, qspi_readl(q, base + QUADSPI_FR), in fsl_qspi_runcmd()
558 qspi_readl(q, base + QUADSPI_SR)); in fsl_qspi_runcmd()
565 qspi_writel(q, reg, base + QUADSPI_MCR); in fsl_qspi_runcmd()
571 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf) in fsl_qspi_read_data() argument
577 tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4); in fsl_qspi_read_data()
578 tmp = fsl_qspi_endian_xchg(q, tmp); in fsl_qspi_read_data()
579 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n", in fsl_qspi_read_data()
580 q->chip_base_addr, tmp); in fsl_qspi_read_data()
601 static inline void fsl_qspi_invalid(struct fsl_qspi *q) in fsl_qspi_invalid() argument
605 reg = qspi_readl(q, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
607 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
616 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
619 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor, in fsl_qspi_nor_write() argument
626 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n", in fsl_qspi_nor_write()
627 q->chip_base_addr, to, count); in fsl_qspi_nor_write()
630 tmp = qspi_readl(q, q->iobase + QUADSPI_MCR); in fsl_qspi_nor_write()
631 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_nor_write()
635 tmp = fsl_qspi_endian_xchg(q, *txbuf); in fsl_qspi_nor_write()
636 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
641 if (needs_fill_txfifo(q)) in fsl_qspi_nor_write()
643 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
646 ret = fsl_qspi_runcmd(q, opcode, to, count); in fsl_qspi_nor_write()
654 static void fsl_qspi_set_map_addr(struct fsl_qspi *q) in fsl_qspi_set_map_addr() argument
656 int nor_size = q->nor_size; in fsl_qspi_set_map_addr()
657 void __iomem *base = q->iobase; in fsl_qspi_set_map_addr()
659 qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); in fsl_qspi_set_map_addr()
660 qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); in fsl_qspi_set_map_addr()
661 qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); in fsl_qspi_set_map_addr()
662 qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); in fsl_qspi_set_map_addr()
678 static int fsl_qspi_init_ahb_read(struct fsl_qspi *q) in fsl_qspi_init_ahb_read() argument
680 void __iomem *base = q->iobase; in fsl_qspi_init_ahb_read()
684 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); in fsl_qspi_init_ahb_read()
685 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); in fsl_qspi_init_ahb_read()
686 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); in fsl_qspi_init_ahb_read()
691 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | in fsl_qspi_init_ahb_read()
692 ((q->devtype_data->ahb_buf_size / 8) in fsl_qspi_init_ahb_read()
697 qspi_writel(q, 0, base + QUADSPI_BUF0IND); in fsl_qspi_init_ahb_read()
698 qspi_writel(q, 0, base + QUADSPI_BUF1IND); in fsl_qspi_init_ahb_read()
699 qspi_writel(q, 0, base + QUADSPI_BUF2IND); in fsl_qspi_init_ahb_read()
702 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); in fsl_qspi_init_ahb_read()
706 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT, in fsl_qspi_init_ahb_read()
707 q->iobase + QUADSPI_BFGENCR); in fsl_qspi_init_ahb_read()
713 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) in fsl_qspi_clk_prep_enable() argument
717 ret = clk_prepare_enable(q->clk_en); in fsl_qspi_clk_prep_enable()
721 ret = clk_prepare_enable(q->clk); in fsl_qspi_clk_prep_enable()
723 clk_disable_unprepare(q->clk_en); in fsl_qspi_clk_prep_enable()
727 if (needs_wakeup_wait_mode(q)) in fsl_qspi_clk_prep_enable()
728 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0); in fsl_qspi_clk_prep_enable()
734 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) in fsl_qspi_clk_disable_unprep() argument
736 if (needs_wakeup_wait_mode(q)) in fsl_qspi_clk_disable_unprep()
737 pm_qos_remove_request(&q->pm_qos_req); in fsl_qspi_clk_disable_unprep()
739 clk_disable_unprepare(q->clk); in fsl_qspi_clk_disable_unprep()
740 clk_disable_unprepare(q->clk_en); in fsl_qspi_clk_disable_unprep()
745 static int fsl_qspi_nor_setup(struct fsl_qspi *q) in fsl_qspi_nor_setup() argument
747 void __iomem *base = q->iobase; in fsl_qspi_nor_setup()
752 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_nor_setup()
755 ret = clk_set_rate(q->clk, 66000000); in fsl_qspi_nor_setup()
759 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_nor_setup()
764 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, in fsl_qspi_nor_setup()
769 fsl_qspi_init_lut(q); in fsl_qspi_nor_setup()
772 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, in fsl_qspi_nor_setup()
775 reg = qspi_readl(q, base + QUADSPI_SMPR); in fsl_qspi_nor_setup()
776 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK in fsl_qspi_nor_setup()
782 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, in fsl_qspi_nor_setup()
786 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR); in fsl_qspi_nor_setup()
789 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); in fsl_qspi_nor_setup()
794 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q) in fsl_qspi_nor_setup_last() argument
796 unsigned long rate = q->clk_rate; in fsl_qspi_nor_setup_last()
799 if (needs_4x_clock(q)) in fsl_qspi_nor_setup_last()
803 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_nor_setup_last()
805 ret = clk_set_rate(q->clk, rate); in fsl_qspi_nor_setup_last()
809 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_nor_setup_last()
814 fsl_qspi_init_lut(q); in fsl_qspi_nor_setup_last()
817 return fsl_qspi_init_ahb_read(q); in fsl_qspi_nor_setup_last()
831 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor) in fsl_qspi_set_base_addr() argument
833 q->chip_base_addr = q->nor_size * (nor - q->nor); in fsl_qspi_set_base_addr()
839 struct fsl_qspi *q = nor->priv; in fsl_qspi_read_reg() local
841 ret = fsl_qspi_runcmd(q, opcode, 0, len); in fsl_qspi_read_reg()
845 fsl_qspi_read_data(q, len, buf); in fsl_qspi_read_reg()
851 struct fsl_qspi *q = nor->priv; in fsl_qspi_write_reg() local
855 ret = fsl_qspi_runcmd(q, opcode, 0, 1); in fsl_qspi_write_reg()
860 fsl_qspi_invalid(q); in fsl_qspi_write_reg()
863 ret = fsl_qspi_nor_write(q, nor, opcode, 0, in fsl_qspi_write_reg()
868 dev_err(q->dev, "invalid cmd %d\n", opcode); in fsl_qspi_write_reg()
878 struct fsl_qspi *q = nor->priv; in fsl_qspi_write() local
879 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to, in fsl_qspi_write()
883 fsl_qspi_invalid(q); in fsl_qspi_write()
890 struct fsl_qspi *q = nor->priv; in fsl_qspi_read() local
894 if (!q->ahb_addr) { in fsl_qspi_read()
895 q->memmap_offs = q->chip_base_addr + from; in fsl_qspi_read()
896 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP; in fsl_qspi_read()
898 q->ahb_addr = ioremap_nocache( in fsl_qspi_read()
899 q->memmap_phy + q->memmap_offs, in fsl_qspi_read()
900 q->memmap_len); in fsl_qspi_read()
901 if (!q->ahb_addr) { in fsl_qspi_read()
902 dev_err(q->dev, "ioremap failed\n"); in fsl_qspi_read()
906 } else if (q->chip_base_addr + from < q->memmap_offs in fsl_qspi_read()
907 || q->chip_base_addr + from + len > in fsl_qspi_read()
908 q->memmap_offs + q->memmap_len) { in fsl_qspi_read()
909 iounmap(q->ahb_addr); in fsl_qspi_read()
911 q->memmap_offs = q->chip_base_addr + from; in fsl_qspi_read()
912 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP; in fsl_qspi_read()
913 q->ahb_addr = ioremap_nocache( in fsl_qspi_read()
914 q->memmap_phy + q->memmap_offs, in fsl_qspi_read()
915 q->memmap_len); in fsl_qspi_read()
916 if (!q->ahb_addr) { in fsl_qspi_read()
917 dev_err(q->dev, "ioremap failed\n"); in fsl_qspi_read()
922 dev_dbg(q->dev, "cmd [%x],read from %p, len:%zd\n", in fsl_qspi_read()
923 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, in fsl_qspi_read()
927 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs, in fsl_qspi_read()
935 struct fsl_qspi *q = nor->priv; in fsl_qspi_erase() local
939 nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs); in fsl_qspi_erase()
941 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0); in fsl_qspi_erase()
945 fsl_qspi_invalid(q); in fsl_qspi_erase()
951 struct fsl_qspi *q = nor->priv; in fsl_qspi_prep() local
954 mutex_lock(&q->lock); in fsl_qspi_prep()
956 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_prep()
960 fsl_qspi_set_base_addr(q, nor); in fsl_qspi_prep()
964 mutex_unlock(&q->lock); in fsl_qspi_prep()
970 struct fsl_qspi *q = nor->priv; in fsl_qspi_unprep() local
972 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_unprep()
973 mutex_unlock(&q->lock); in fsl_qspi_unprep()
984 struct fsl_qspi *q; in fsl_qspi_probe() local
990 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL); in fsl_qspi_probe()
991 if (!q) in fsl_qspi_probe()
994 q->nor_num = of_get_child_count(dev->of_node); in fsl_qspi_probe()
995 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP) in fsl_qspi_probe()
998 q->dev = dev; in fsl_qspi_probe()
999 q->devtype_data = of_device_get_match_data(dev); in fsl_qspi_probe()
1000 if (!q->devtype_data) in fsl_qspi_probe()
1002 platform_set_drvdata(pdev, q); in fsl_qspi_probe()
1006 q->iobase = devm_ioremap_resource(dev, res); in fsl_qspi_probe()
1007 if (IS_ERR(q->iobase)) in fsl_qspi_probe()
1008 return PTR_ERR(q->iobase); in fsl_qspi_probe()
1010 q->big_endian = of_property_read_bool(np, "big-endian"); in fsl_qspi_probe()
1019 q->memmap_phy = res->start; in fsl_qspi_probe()
1022 q->clk_en = devm_clk_get(dev, "qspi_en"); in fsl_qspi_probe()
1023 if (IS_ERR(q->clk_en)) in fsl_qspi_probe()
1024 return PTR_ERR(q->clk_en); in fsl_qspi_probe()
1026 q->clk = devm_clk_get(dev, "qspi"); in fsl_qspi_probe()
1027 if (IS_ERR(q->clk)) in fsl_qspi_probe()
1028 return PTR_ERR(q->clk); in fsl_qspi_probe()
1030 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_probe()
1044 fsl_qspi_irq_handler, 0, pdev->name, q); in fsl_qspi_probe()
1050 ret = fsl_qspi_nor_setup(q); in fsl_qspi_probe()
1055 q->has_second_chip = true; in fsl_qspi_probe()
1057 mutex_init(&q->lock); in fsl_qspi_probe()
1062 if (!q->has_second_chip) in fsl_qspi_probe()
1065 nor = &q->nor[i]; in fsl_qspi_probe()
1070 nor->priv = q; in fsl_qspi_probe()
1072 if (q->nor_num > 1 && !mtd->name) { in fsl_qspi_probe()
1101 &q->clk_rate); in fsl_qspi_probe()
1106 fsl_qspi_set_base_addr(q, nor); in fsl_qspi_probe()
1117 if (q->nor_size == 0) { in fsl_qspi_probe()
1118 q->nor_size = mtd->size; in fsl_qspi_probe()
1121 fsl_qspi_set_map_addr(q); in fsl_qspi_probe()
1133 if (nor->page_size > q->devtype_data->txfifo) in fsl_qspi_probe()
1134 nor->page_size = q->devtype_data->txfifo; in fsl_qspi_probe()
1140 ret = fsl_qspi_nor_setup_last(q); in fsl_qspi_probe()
1144 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_probe()
1148 for (i = 0; i < q->nor_num; i++) { in fsl_qspi_probe()
1150 if (!q->has_second_chip) in fsl_qspi_probe()
1152 mtd_device_unregister(&q->nor[i].mtd); in fsl_qspi_probe()
1155 mutex_destroy(&q->lock); in fsl_qspi_probe()
1157 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_probe()
1165 struct fsl_qspi *q = platform_get_drvdata(pdev); in fsl_qspi_remove() local
1168 for (i = 0; i < q->nor_num; i++) { in fsl_qspi_remove()
1170 if (!q->has_second_chip) in fsl_qspi_remove()
1172 mtd_device_unregister(&q->nor[i].mtd); in fsl_qspi_remove()
1176 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_remove()
1177 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); in fsl_qspi_remove()
1179 mutex_destroy(&q->lock); in fsl_qspi_remove()
1181 if (q->ahb_addr) in fsl_qspi_remove()
1182 iounmap(q->ahb_addr); in fsl_qspi_remove()
1195 struct fsl_qspi *q = platform_get_drvdata(pdev); in fsl_qspi_resume() local
1197 ret = fsl_qspi_clk_prep_enable(q); in fsl_qspi_resume()
1201 fsl_qspi_nor_setup(q); in fsl_qspi_resume()
1202 fsl_qspi_set_map_addr(q); in fsl_qspi_resume()
1203 fsl_qspi_nor_setup_last(q); in fsl_qspi_resume()
1205 fsl_qspi_clk_disable_unprep(q); in fsl_qspi_resume()