4  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
29 #include <linux/mtd/spi-nor.h>
124 #define FSIZE_VAL(size)		(__fls(size) - 1)
138 	u32 presc;  member
179 	if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)  in stm32_qspi_wait_cmd()
182 	reinit_completion(&qspi->cmd_completion);  in stm32_qspi_wait_cmd()
183 	cr = readl_relaxed(qspi->io_base + QUADSPI_CR);  in stm32_qspi_wait_cmd()
184 	writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);  in stm32_qspi_wait_cmd()
186 	if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,  in stm32_qspi_wait_cmd()
188 		err = -ETIMEDOUT;  in stm32_qspi_wait_cmd()
190 	writel_relaxed(cr, qspi->io_base + QUADSPI_CR);  in stm32_qspi_wait_cmd()
198 	return readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR, sr,  in stm32_qspi_wait_nobusy()
208 	cmd->framemode = CCR_IMODE_1;  in stm32_qspi_set_framemode()
211 		switch (nor->read_proto) {  in stm32_qspi_set_framemode()
225 	cmd->framemode |= cmd->tx_data ? dmode : 0;  in stm32_qspi_set_framemode()
226 	cmd->framemode |= cmd->addr_width ? CCR_ADMODE_1 : 0;  in stm32_qspi_set_framemode()
243 	u32 len = cmd->len, sr;  in stm32_qspi_tx_poll()
244 	u8 *buf = cmd->buf;  in stm32_qspi_tx_poll()
247 	if (cmd->qspimode == CCR_FMODE_INDW)  in stm32_qspi_tx_poll()
252 	while (len--) {  in stm32_qspi_tx_poll()
253 		ret = readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR,  in stm32_qspi_tx_poll()
257 			dev_err(qspi->dev, "fifo timeout (stat:%#x)\n", sr);  in stm32_qspi_tx_poll()
260 		tx_fifo(buf++, qspi->io_base + QUADSPI_DR);  in stm32_qspi_tx_poll()
269 	memcpy_fromio(cmd->buf, qspi->mm_base + cmd->addr, cmd->len);  in stm32_qspi_tx_mm()
276 	if (!cmd->tx_data)  in stm32_qspi_tx()
279 	if (cmd->qspimode == CCR_FMODE_MM)  in stm32_qspi_tx()
288 	struct stm32_qspi *qspi = flash->qspi;  in stm32_qspi_send()
297 	dcr = readl_relaxed(qspi->io_base + QUADSPI_DCR) & ~DCR_FSIZE_MASK;  in stm32_qspi_send()
298 	dcr |= DCR_FSIZE(flash->fsize);  in stm32_qspi_send()
299 	writel_relaxed(dcr, qspi->io_base + QUADSPI_DCR);  in stm32_qspi_send()
301 	cr = readl_relaxed(qspi->io_base + QUADSPI_CR);  in stm32_qspi_send()
303 	cr |= CR_PRESC(flash->presc);  in stm32_qspi_send()
304 	cr |= flash->cs ? CR_FSEL : 0;  in stm32_qspi_send()
305 	writel_relaxed(cr, qspi->io_base + QUADSPI_CR);  in stm32_qspi_send()
307 	if (cmd->tx_data)  in stm32_qspi_send()
308 		writel_relaxed(cmd->len - 1, qspi->io_base + QUADSPI_DLR);  in stm32_qspi_send()
310 	ccr = cmd->framemode | cmd->qspimode;  in stm32_qspi_send()
312 	if (cmd->dummy)  in stm32_qspi_send()
313 		ccr |= CCR_DCYC(cmd->dummy);  in stm32_qspi_send()
315 	if (cmd->addr_width)  in stm32_qspi_send()
316 		ccr |= CCR_ADSIZE(cmd->addr_width - 1);  in stm32_qspi_send()
318 	ccr |= CCR_INST(cmd->opcode);  in stm32_qspi_send()
319 	writel_relaxed(ccr, qspi->io_base + QUADSPI_CCR);  in stm32_qspi_send()
321 	if (cmd->addr_width && cmd->qspimode != CCR_FMODE_MM)  in stm32_qspi_send()
322 		writel_relaxed(cmd->addr, qspi->io_base + QUADSPI_AR);  in stm32_qspi_send()
328 	if (cmd->qspimode != CCR_FMODE_MM) {  in stm32_qspi_send()
332 		writel_relaxed(FCR_CTCF, qspi->io_base + QUADSPI_FCR);  in stm32_qspi_send()
334 		last_byte = cmd->addr + cmd->len;  in stm32_qspi_send()
335 		if (last_byte > flash->prefetch_limit)  in stm32_qspi_send()
342 	cr = readl_relaxed(qspi->io_base + QUADSPI_CR) | CR_ABORT;  in stm32_qspi_send()
343 	writel_relaxed(cr, qspi->io_base + QUADSPI_CR);  in stm32_qspi_send()
346 		dev_err(qspi->dev, "%s abort err:%d\n", __func__, err);  in stm32_qspi_send()
354 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_read_reg()
355 	struct device *dev = flash->qspi->dev;  in stm32_qspi_read_reg()
375 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_write_reg()
376 	struct device *dev = flash->qspi->dev;  in stm32_qspi_write_reg()
396 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_read()
397 	struct stm32_qspi *qspi = flash->qspi;  in stm32_qspi_read()
401 	dev_dbg(qspi->dev, "read(%#.2x): buf:%pK from:%#.8x len:%#zx\n",  in stm32_qspi_read()
402 		nor->read_opcode, buf, (u32)from, len);  in stm32_qspi_read()
405 	cmd.opcode = nor->read_opcode;  in stm32_qspi_read()
406 	cmd.addr_width = nor->addr_width;  in stm32_qspi_read()
409 	cmd.dummy = nor->read_dummy;  in stm32_qspi_read()
412 	cmd.qspimode = flash->read_mode;  in stm32_qspi_read()
423 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_write()
424 	struct device *dev = flash->qspi->dev;  in stm32_qspi_write()
429 		nor->program_opcode, buf, (u32)to, len);  in stm32_qspi_write()
432 	cmd.opcode = nor->program_opcode;  in stm32_qspi_write()
433 	cmd.addr_width = nor->addr_width;  in stm32_qspi_write()
448 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_erase()
449 	struct device *dev = flash->qspi->dev;  in stm32_qspi_erase()
452 	dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);  in stm32_qspi_erase()
455 	cmd.opcode = nor->erase_opcode;  in stm32_qspi_erase()
456 	cmd.addr_width = nor->addr_width;  in stm32_qspi_erase()
470 	cr = readl_relaxed(qspi->io_base + QUADSPI_CR);  in stm32_qspi_irq()
471 	sr = readl_relaxed(qspi->io_base + QUADSPI_SR);  in stm32_qspi_irq()
476 		complete(&qspi->cmd_completion);  in stm32_qspi_irq()
478 		dev_info_ratelimited(qspi->dev, "spurious interrupt\n");  in stm32_qspi_irq()
481 	writel_relaxed(fcr, qspi->io_base + QUADSPI_FCR);  in stm32_qspi_irq()
488 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_prep()
489 	struct stm32_qspi *qspi = flash->qspi;  in stm32_qspi_prep()
491 	mutex_lock(&qspi->lock);  in stm32_qspi_prep()
497 	struct stm32_qspi_flash *flash = nor->priv;  in stm32_qspi_unprep()
498 	struct stm32_qspi *qspi = flash->qspi;  in stm32_qspi_unprep()
500 	mutex_unlock(&qspi->lock);  in stm32_qspi_unprep()
511 	u32 width, presc, cs_num, max_rate = 0;  in stm32_qspi_flash_setup()  local
518 		return -EINVAL;  in stm32_qspi_flash_setup()
520 	of_property_read_u32(np, "spi-max-frequency", &max_rate);  in stm32_qspi_flash_setup()
522 		return -EINVAL;  in stm32_qspi_flash_setup()
524 	presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;  in stm32_qspi_flash_setup()
526 	if (of_property_read_u32(np, "spi-rx-bus-width", &width))  in stm32_qspi_flash_setup()
534 		return -EINVAL;  in stm32_qspi_flash_setup()
536 	flash = &qspi->flash[cs_num];  in stm32_qspi_flash_setup()
537 	flash->qspi = qspi;  in stm32_qspi_flash_setup()
538 	flash->cs = cs_num;  in stm32_qspi_flash_setup()
539 	flash->presc = presc;  in stm32_qspi_flash_setup()
541 	flash->nor.dev = qspi->dev;  in stm32_qspi_flash_setup()
542 	spi_nor_set_flash_node(&flash->nor, np);  in stm32_qspi_flash_setup()
543 	flash->nor.priv = flash;  in stm32_qspi_flash_setup()
544 	mtd = &flash->nor.mtd;  in stm32_qspi_flash_setup()
546 	flash->nor.read = stm32_qspi_read;  in stm32_qspi_flash_setup()
547 	flash->nor.write = stm32_qspi_write;  in stm32_qspi_flash_setup()
548 	flash->nor.erase = stm32_qspi_erase;  in stm32_qspi_flash_setup()
549 	flash->nor.read_reg = stm32_qspi_read_reg;  in stm32_qspi_flash_setup()
550 	flash->nor.write_reg = stm32_qspi_write_reg;  in stm32_qspi_flash_setup()
551 	flash->nor.prepare = stm32_qspi_prep;  in stm32_qspi_flash_setup()
552 	flash->nor.unprepare = stm32_qspi_unprep;  in stm32_qspi_flash_setup()
554 	writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QUADSPI_LPTR);  in stm32_qspi_flash_setup()
556 	writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | CR_SSHIFT  in stm32_qspi_flash_setup()
557 		       | CR_EN, qspi->io_base + QUADSPI_CR);  in stm32_qspi_flash_setup()
562 	 * if fsize is NULL, the controller can't sent spi-nor command.  in stm32_qspi_flash_setup()
564 	 * "spi_nor_scan". After, the right value (mtd->size) can be set.  in stm32_qspi_flash_setup()
566 	flash->fsize = FSIZE_VAL(SZ_1K);  in stm32_qspi_flash_setup()
568 	ret = spi_nor_scan(&flash->nor, NULL, &hwcaps);  in stm32_qspi_flash_setup()
570 		dev_err(qspi->dev, "device scan failed\n");  in stm32_qspi_flash_setup()
574 	flash->fsize = FSIZE_VAL(mtd->size);  in stm32_qspi_flash_setup()
575 	flash->prefetch_limit = mtd->size - STM32_QSPI_FIFO_SZ;  in stm32_qspi_flash_setup()
577 	flash->read_mode = CCR_FMODE_MM;  in stm32_qspi_flash_setup()
578 	if (mtd->size > qspi->mm_size)  in stm32_qspi_flash_setup()
579 		flash->read_mode = CCR_FMODE_INDR;  in stm32_qspi_flash_setup()
581 	writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);  in stm32_qspi_flash_setup()
585 		dev_err(qspi->dev, "mtd device parse failed\n");  in stm32_qspi_flash_setup()
589 	flash->registered = true;  in stm32_qspi_flash_setup()
591 	dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",  in stm32_qspi_flash_setup()
592 		flash->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);  in stm32_qspi_flash_setup()
602 		if (qspi->flash[i].registered)  in stm32_qspi_mtd_free()
603 			mtd_device_unregister(&qspi->flash[i].nor.mtd);  in stm32_qspi_mtd_free()
608 	struct device *dev = &pdev->dev;  in stm32_qspi_probe()
617 		return -ENOMEM;  in stm32_qspi_probe()
619 	qspi->nor_num = of_get_child_count(dev->of_node);  in stm32_qspi_probe()
620 	if (!qspi->nor_num || qspi->nor_num > STM32_MAX_NORCHIP)  in stm32_qspi_probe()
621 		return -ENODEV;  in stm32_qspi_probe()
624 	qspi->io_base = devm_ioremap_resource(dev, res);  in stm32_qspi_probe()
625 	if (IS_ERR(qspi->io_base))  in stm32_qspi_probe()
626 		return PTR_ERR(qspi->io_base);  in stm32_qspi_probe()
629 	qspi->mm_base = devm_ioremap_resource(dev, res);  in stm32_qspi_probe()
630 	if (IS_ERR(qspi->mm_base))  in stm32_qspi_probe()
631 		return PTR_ERR(qspi->mm_base);  in stm32_qspi_probe()
633 	qspi->mm_size = resource_size(res);  in stm32_qspi_probe()
643 	init_completion(&qspi->cmd_completion);  in stm32_qspi_probe()
645 	qspi->clk = devm_clk_get(dev, NULL);  in stm32_qspi_probe()
646 	if (IS_ERR(qspi->clk))  in stm32_qspi_probe()
647 		return PTR_ERR(qspi->clk);  in stm32_qspi_probe()
649 	qspi->clk_rate = clk_get_rate(qspi->clk);  in stm32_qspi_probe()
650 	if (!qspi->clk_rate)  in stm32_qspi_probe()
651 		return -EINVAL;  in stm32_qspi_probe()
653 	ret = clk_prepare_enable(qspi->clk);  in stm32_qspi_probe()
655 		dev_err(dev, "can not enable the clock\n");  in stm32_qspi_probe()
666 	qspi->dev = dev;  in stm32_qspi_probe()
668 	mutex_init(&qspi->lock);  in stm32_qspi_probe()
670 	for_each_available_child_of_node(dev->of_node, flash_np) {  in stm32_qspi_probe()
681 	mutex_destroy(&qspi->lock);  in stm32_qspi_probe()
684 	clk_disable_unprepare(qspi->clk);  in stm32_qspi_probe()
693 	writel_relaxed(0, qspi->io_base + QUADSPI_CR);  in stm32_qspi_remove()
696 	mutex_destroy(&qspi->lock);  in stm32_qspi_remove()
698 	clk_disable_unprepare(qspi->clk);  in stm32_qspi_remove()
703 	{.compatible = "st,stm32f469-qspi"},
712 		.name = "stm32-quadspi",