Lines Matching +full:even +full:- +full:numbered
7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
14 * kind, whether express or implied; without even the implied warranty
44 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
45 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
64 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
65 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
66 #define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1))
71 * RX mailboxes are further logically split into two - main and buffer
75 * processed. This ensures in-order packet reception.
85 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
87 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
88 #define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
115 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
116 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
132 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
134 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
212 return priv->tx_head & HECC_TX_MB_MASK; in get_tx_head_mb()
217 return priv->tx_tail & HECC_TX_MB_MASK; in get_tx_tail_mb()
222 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; in get_tx_head_prio()
227 __raw_writel(val, priv->hecc_ram + mbxno * 4); in hecc_write_lam()
233 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); in hecc_write_mbx()
238 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); in hecc_read_mbx()
243 __raw_writel(val, priv->base + reg); in hecc_write()
248 return __raw_readl(priv->base + reg); in hecc_read()
270 struct can_bittiming *bit_timing = &priv->can.bittiming; in ti_hecc_set_btc()
273 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; in ti_hecc_set_btc()
274 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) in ti_hecc_set_btc()
276 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { in ti_hecc_set_btc()
277 if (bit_timing->brp > 4) in ti_hecc_set_btc()
280 netdev_warn(priv->ndev, "WARN: Triple" in ti_hecc_set_btc()
283 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; in ti_hecc_set_btc()
284 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; in ti_hecc_set_btc()
289 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); in ti_hecc_set_btc()
297 if (!priv->reg_xceiver) in ti_hecc_transceiver_switch()
301 return regulator_enable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
303 return regulator_disable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
319 * set and hw seems to be ok even if this bit is not set so in ti_hecc_reset()
324 --cnt; in ti_hecc_reset()
339 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on in ti_hecc_reset()
345 * set and hw seems to be ok even if this bit is not set so in ti_hecc_reset()
349 --cnt; in ti_hecc_reset()
377 priv->tx_head = priv->tx_tail = HECC_TX_MASK; in ti_hecc_start()
378 priv->rx_next = HECC_RX_FIRST_MBOX; in ti_hecc_start()
385 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; in ti_hecc_start()
395 /* Prevent message over-write & Enable interrupts */ in ti_hecc_start()
397 if (priv->use_hecc1int) { in ti_hecc_start()
406 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_start()
417 priv->can.state = CAN_STATE_STOPPED; in ti_hecc_stop()
430 ret = -EOPNOTSUPP; in ti_hecc_do_set_mode()
442 bec->txerr = hecc_read(priv, HECC_CANTEC); in ti_hecc_get_berr_counter()
443 bec->rxerr = hecc_read(priv, HECC_CANREC); in ti_hecc_get_berr_counter()
455 * priority field the highest numbered mailbox is transmitted first.
458 * highest numbered mailbox with highest priority level and move on to the next
461 * until we reach the lowest priority level on the lowest numbered mailbox
463 * restart at highest numbered mailbox with highest priority.
468 * value roll-over happens.
473 struct can_frame *cf = (struct can_frame *)skb->data; in ti_hecc_xmit()
482 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
484 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
486 netdev_err(priv->ndev, in ti_hecc_xmit()
488 priv->tx_head, priv->tx_tail); in ti_hecc_xmit()
491 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
494 data = cf->can_dlc | (get_tx_head_prio(priv) << 8); in ti_hecc_xmit()
495 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ in ti_hecc_xmit()
499 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ in ti_hecc_xmit()
500 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; in ti_hecc_xmit()
502 data = (cf->can_id & CAN_SFF_MASK) << 18; in ti_hecc_xmit()
505 be32_to_cpu(*(__be32 *)(cf->data))); in ti_hecc_xmit()
506 if (cf->can_dlc > 4) in ti_hecc_xmit()
508 be32_to_cpu(*(__be32 *)(cf->data + 4))); in ti_hecc_xmit()
510 *(u32 *)(cf->data + 4) = 0; in ti_hecc_xmit()
513 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
514 --priv->tx_head; in ti_hecc_xmit()
516 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { in ti_hecc_xmit()
520 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
531 struct net_device_stats *stats = &priv->ndev->stats; in ti_hecc_rx_pkt()
537 skb = alloc_can_skb(priv->ndev, &cf); in ti_hecc_rx_pkt()
540 netdev_err(priv->ndev, in ti_hecc_rx_pkt()
542 return -ENOMEM; in ti_hecc_rx_pkt()
548 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; in ti_hecc_rx_pkt()
550 cf->can_id = (data >> 18) & CAN_SFF_MASK; in ti_hecc_rx_pkt()
553 cf->can_id |= CAN_RTR_FLAG; in ti_hecc_rx_pkt()
554 cf->can_dlc = get_can_dlc(data & 0xF); in ti_hecc_rx_pkt()
556 *(__be32 *)(cf->data) = cpu_to_be32(data); in ti_hecc_rx_pkt()
557 if (cf->can_dlc > 4) { in ti_hecc_rx_pkt()
559 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); in ti_hecc_rx_pkt()
561 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_rx_pkt()
565 if (priv->rx_next < HECC_RX_BUFFER_MBOX) in ti_hecc_rx_pkt()
567 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_rx_pkt()
569 stats->rx_bytes += cf->can_dlc; in ti_hecc_rx_pkt()
570 can_led_event(priv->ndev, CAN_LED_EVENT_RX); in ti_hecc_rx_pkt()
572 stats->rx_packets++; in ti_hecc_rx_pkt()
578 * ti_hecc_rx_poll - HECC receive pkts
580 * The receive mailboxes start from highest numbered mailbox till last xmit
582 * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
584 * available RX mailbox and we need to ensure in-order packet reception.
600 struct net_device *ndev = napi->dev; in ti_hecc_rx_poll()
611 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */ in ti_hecc_rx_poll()
613 if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0) in ti_hecc_rx_poll()
616 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) { in ti_hecc_rx_poll()
619 --priv->rx_next; in ti_hecc_rx_poll()
620 if (priv->rx_next == HECC_RX_BUFFER_MBOX) { in ti_hecc_rx_poll()
622 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_rx_poll()
626 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_rx_poll()
627 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) { in ti_hecc_rx_poll()
628 priv->rx_next = HECC_RX_FIRST_MBOX; in ti_hecc_rx_poll()
636 /* Re-enable RX mailbox interrupts */ in ti_hecc_rx_poll()
652 struct net_device_stats *stats = &ndev->stats; in ti_hecc_error()
660 netdev_err(priv->ndev, in ti_hecc_error()
662 return -ENOMEM; in ti_hecc_error()
667 priv->can.state = CAN_STATE_ERROR_WARNING; in ti_hecc_error()
668 ++priv->can.can_stats.error_warning; in ti_hecc_error()
669 cf->can_id |= CAN_ERR_CRTL; in ti_hecc_error()
671 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; in ti_hecc_error()
673 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; in ti_hecc_error()
676 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); in ti_hecc_error()
682 priv->can.state = CAN_STATE_ERROR_PASSIVE; in ti_hecc_error()
683 ++priv->can.can_stats.error_passive; in ti_hecc_error()
684 cf->can_id |= CAN_ERR_CRTL; in ti_hecc_error()
686 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; in ti_hecc_error()
688 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; in ti_hecc_error()
691 netdev_dbg(priv->ndev, "Error passive interrupt\n"); in ti_hecc_error()
700 priv->can.state = CAN_STATE_BUS_OFF; in ti_hecc_error()
701 cf->can_id |= CAN_ERR_BUSOFF; in ti_hecc_error()
704 /* Disable all interrupts in bus-off to avoid int hog */ in ti_hecc_error()
706 ++priv->can.can_stats.bus_off; in ti_hecc_error()
711 ++priv->can.can_stats.bus_error; in ti_hecc_error()
712 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; in ti_hecc_error()
715 cf->data[2] |= CAN_ERR_PROT_FORM; in ti_hecc_error()
719 cf->data[2] |= CAN_ERR_PROT_BIT; in ti_hecc_error()
723 cf->data[2] |= CAN_ERR_PROT_STUFF; in ti_hecc_error()
727 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in ti_hecc_error()
731 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in ti_hecc_error()
735 stats->rx_packets++; in ti_hecc_error()
736 stats->rx_bytes += cf->can_dlc; in ti_hecc_error()
746 struct net_device_stats *stats = &ndev->stats; in ti_hecc_interrupt()
751 (priv->use_hecc1int) ? HECC_CANGIF1 : HECC_CANGIF0); in ti_hecc_interrupt()
762 while (priv->tx_tail - priv->tx_head > 0) { in ti_hecc_interrupt()
769 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_interrupt()
771 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_interrupt()
772 stats->tx_bytes += hecc_read_mbx(priv, mbxno, in ti_hecc_interrupt()
774 stats->tx_packets++; in ti_hecc_interrupt()
777 --priv->tx_tail; in ti_hecc_interrupt()
780 /* restart queue if wrap-up or if queue stalled on last pkt */ in ti_hecc_interrupt()
781 if (((priv->tx_head == priv->tx_tail) && in ti_hecc_interrupt()
782 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || in ti_hecc_interrupt()
783 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && in ti_hecc_interrupt()
784 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) in ti_hecc_interrupt()
790 ack &= BIT(HECC_MAX_TX_MBOX) - 1; in ti_hecc_interrupt()
792 napi_schedule(&priv->napi); in ti_hecc_interrupt()
796 /* clear all interrupt conditions - read back to avoid spurious ints */ in ti_hecc_interrupt()
797 if (priv->use_hecc1int) { in ti_hecc_interrupt()
813 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, in ti_hecc_open()
814 ndev->name, ndev); in ti_hecc_open()
827 free_irq(ndev->irq, ndev); in ti_hecc_open()
834 napi_enable(&priv->napi); in ti_hecc_open()
845 napi_disable(&priv->napi); in ti_hecc_close()
847 free_irq(ndev->irq, ndev); in ti_hecc_close()
865 .compatible = "ti,am3517-hecc",
875 struct device_node *np = pdev->dev.of_node; in ti_hecc_probe()
878 int err = -ENODEV; in ti_hecc_probe()
881 return -EINVAL; in ti_hecc_probe()
883 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); in ti_hecc_probe()
884 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in ti_hecc_probe()
885 return -EPROBE_DEFER; in ti_hecc_probe()
891 dev_err(&pdev->dev, "alloc_candev failed\n"); in ti_hecc_probe()
892 return -ENOMEM; in ti_hecc_probe()
899 dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc\n"); in ti_hecc_probe()
900 return -EINVAL; in ti_hecc_probe()
903 priv->base = devm_ioremap_resource(&pdev->dev, res); in ti_hecc_probe()
904 if (IS_ERR(priv->base)) { in ti_hecc_probe()
905 dev_err(&pdev->dev, "hecc ioremap failed\n"); in ti_hecc_probe()
906 return PTR_ERR(priv->base); in ti_hecc_probe()
909 /* handle hecc-ram memory */ in ti_hecc_probe()
910 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc-ram"); in ti_hecc_probe()
912 dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc-ram\n"); in ti_hecc_probe()
913 return -EINVAL; in ti_hecc_probe()
916 priv->hecc_ram = devm_ioremap_resource(&pdev->dev, res); in ti_hecc_probe()
917 if (IS_ERR(priv->hecc_ram)) { in ti_hecc_probe()
918 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); in ti_hecc_probe()
919 return PTR_ERR(priv->hecc_ram); in ti_hecc_probe()
925 dev_err(&pdev->dev, "can't get IORESOURCE_MEM mbx\n"); in ti_hecc_probe()
926 return -EINVAL; in ti_hecc_probe()
929 priv->mbx = devm_ioremap_resource(&pdev->dev, res); in ti_hecc_probe()
930 if (IS_ERR(priv->mbx)) { in ti_hecc_probe()
931 dev_err(&pdev->dev, "mbx ioremap failed\n"); in ti_hecc_probe()
932 return PTR_ERR(priv->mbx); in ti_hecc_probe()
937 dev_err(&pdev->dev, "No irq resource\n"); in ti_hecc_probe()
941 priv->ndev = ndev; in ti_hecc_probe()
942 priv->reg_xceiver = reg_xceiver; in ti_hecc_probe()
943 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); in ti_hecc_probe()
945 priv->can.bittiming_const = &ti_hecc_bittiming_const; in ti_hecc_probe()
946 priv->can.do_set_mode = ti_hecc_do_set_mode; in ti_hecc_probe()
947 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; in ti_hecc_probe()
948 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; in ti_hecc_probe()
950 spin_lock_init(&priv->mbx_lock); in ti_hecc_probe()
951 ndev->irq = irq->start; in ti_hecc_probe()
952 ndev->flags |= IFF_ECHO; in ti_hecc_probe()
954 SET_NETDEV_DEV(ndev, &pdev->dev); in ti_hecc_probe()
955 ndev->netdev_ops = &ti_hecc_netdev_ops; in ti_hecc_probe()
957 priv->clk = clk_get(&pdev->dev, "hecc_ck"); in ti_hecc_probe()
958 if (IS_ERR(priv->clk)) { in ti_hecc_probe()
959 dev_err(&pdev->dev, "No clock available\n"); in ti_hecc_probe()
960 err = PTR_ERR(priv->clk); in ti_hecc_probe()
961 priv->clk = NULL; in ti_hecc_probe()
964 priv->can.clock.freq = clk_get_rate(priv->clk); in ti_hecc_probe()
965 netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll, in ti_hecc_probe()
968 err = clk_prepare_enable(priv->clk); in ti_hecc_probe()
970 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); in ti_hecc_probe()
976 dev_err(&pdev->dev, "register_candev() failed\n"); in ti_hecc_probe()
982 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", in ti_hecc_probe()
983 priv->base, (u32) ndev->irq); in ti_hecc_probe()
988 clk_put(priv->clk); in ti_hecc_probe()
1001 clk_disable_unprepare(priv->clk); in ti_hecc_remove()
1002 clk_put(priv->clk); in ti_hecc_remove()
1020 priv->can.state = CAN_STATE_SLEEPING; in ti_hecc_suspend()
1022 clk_disable_unprepare(priv->clk); in ti_hecc_suspend()
1033 err = clk_prepare_enable(priv->clk); in ti_hecc_resume()
1038 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_resume()