Lines Matching full:structure

88 /* structure for power management control status reg in global address map
184 /* structure for txdma packet ring base address hi reg in txdma address map
189 /* structure for txdma packet ring base address low reg in txdma address map
194 /* structure for txdma packet ring number of descriptor reg in txdma address
222  * structure for txdma service complete reg in txdma address map at 0x1028
272 /* structure for control status reg in rxdma address map
301 /* structure for dma writeback lo reg in rxdma address map
306 /* structure for dma writeback hi reg in rxdma address map
311 /* structure for number of packets done reg in rxdma address map
318 /* structure for max packet time reg in rxdma address map
325 /* structure for rx queue read address reg in rxdma address map
330 /* structure for rx queue read address external reg in rxdma address map
335 /* structure for rx queue write address reg in rxdma address map
340 /* structure for packet status ring base address lo reg in rxdma address map
345 /* structure for packet status ring base address hi reg in rxdma address map
350 /* structure for packet status ring number of descriptors reg in rxdma address
358 /* structure for packet status ring available offset reg in rxdma address map
366 /* structure for packet status ring full offset reg in rxdma address map
374 /* structure for packet status ring access index reg in rxdma address map
381 /* structure for packet status ring minimum descriptors reg in rxdma address
388 /* structure for free buffer ring base lo address reg in rxdma address map
393 /* structure for free buffer ring base hi address reg in rxdma address map
398 /* structure for free buffer ring number of descriptors reg in rxdma address
405 /* structure for free buffer ring 0 available offset reg in rxdma address map
410 /* structure for free buffer ring 0 full offset reg in rxdma address map
415 /* structure for free buffer cache 0 full offset reg in rxdma address map
422 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
429 /* structure for free buffer ring 1 base address lo reg in rxdma address map
434 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
439 /* structure for free buffer ring 1 available offset reg in rxdma address map
444 /* structure for free buffer ring 1 full offset reg in rxdma address map
449 /* structure for free buffer cache 1 read index reg in rxdma address map
454 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
497 /* structure for control reg in txmac address map
514 /* structure for shadow pointer reg in txmac address map
522 /* structure for error count reg in txmac address map
531 /* structure for max fill reg in txmac address map
537 /* structure for cf parameter reg in txmac address map
543 /* structure for tx test reg in txmac address map
552 /* structure for error reg in txmac address map
566 /* structure for error interrupt reg in txmac address map
580 /* structure for error interrupt reg in txmac address map
606 /* structure for rxmac control reg in rxmac address map
621 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
635 /* structure for CRC 1 and CRC 2 reg in rxmac address map
642 /* structure for CRC 3 and CRC 4 reg in rxmac address map
649 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
661 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
670 /* structure for Wake On Lan mask reg in rxmac address map
675 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
687 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
699 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
711 /* structure for Multicast Hash reg in rxmac address map
716 /* structure for Packet Filter Control reg in rxmac address map
733 /* structure for Memory Controller Interface Control Max Segment reg in rxmac
745 /* structure for Memory Controller Interface Water Mark reg in rxmac address
754 /* structure for Rx Queue Dialog reg in rxmac address map.
763 /* structure for space available reg in rxmac address map.
772 /* structure for management interface reg in rxmac address map.
780 /* structure for Error reg in rxmac address map.
839 /* structure for configuration #1 reg in mac address map.
872 /* structure for configuration #2 reg in mac address map.
896 /* structure for Interpacket gap reg in mac address map.
906  * structure for half duplex reg in mac address map.
919 /* structure for Maximum Frame Length reg in mac address map.
923 /* structure for Reserve 1 reg in mac address map.
928 /* structure for Test reg in mac address map.
933 /* structure for MII Management Configuration reg in mac address map.
945 /* structure for MII Management Command reg in mac address map.
951 /* structure for MII Management Address reg in mac address map.
960 /* structure for MII Management Control reg in mac address map.
966 /* structure for MII Management Status reg in mac address map.
973 /* structure for MII Management Indicators reg in mac address map.
983 /* structure for Interface Control reg in mac address map.
1007 /* structure for Interface Status reg in mac address map.
1023 /* structure for Mac Station Address, Part 1 reg in mac address map.
1035 /* structure for Mac Station Address, Part 2 reg in mac address map.
1071 /* structure for Carry Register One and it's Mask Register reg located in mac
1101 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1204 /* structure for Main Memory Controller Host Memory Access Data reg in mmc