Lines Matching +full:dp +full:- +full:phy1
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
97 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
99 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
101 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
129 * and dev->tx_timeout() should be called to fix the problem
152 /* Do not place this n-ring entries value into the tp struct itself,
156 * replace things like '% foo' with '& (foo - 1)'.
160 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
167 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
170 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
203 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
207 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
213 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
241 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
363 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
481 writel(val, tp->regs + off); in tg3_write32()
486 return readl(tp->regs + off); in tg3_read32()
491 writel(val, tp->aperegs + off); in tg3_ape_write32()
496 return readl(tp->aperegs + off); in tg3_ape_read32()
503 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
504 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
506 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
511 writel(val, tp->regs + off); in tg3_write_flush_reg32()
512 readl(tp->regs + off); in tg3_write_flush_reg32()
520 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
521 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
522 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
523 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
532 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
537 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
542 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
543 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
544 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
545 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
552 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
553 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
562 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
563 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
564 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
565 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
577 /* Non-posted methods */ in _tw32_flush()
578 tp->write32(tp, off, val); in _tw32_flush()
584 tp->read32(tp, off); in _tw32_flush()
595 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
599 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
604 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
615 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
620 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
623 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
625 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
626 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
627 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
629 #define tw32(reg, val) tp->write32(tp, reg, val)
632 #define tr32(reg) tp->read32(tp, reg)
642 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
644 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
645 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
648 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
656 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
669 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
671 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
672 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
675 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
683 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
706 if (!tp->pci_fn) in tg3_ape_lock_init()
709 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
732 if (!tp->pci_fn) in tg3_ape_lock()
735 bit = 1 << tp->pci_fn; in tg3_ape_lock()
744 return -EINVAL; in tg3_ape_lock()
764 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
773 ret = -EBUSY; in tg3_ape_lock()
793 if (!tp->pci_fn) in tg3_ape_unlock()
796 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
822 return -EBUSY; in tg3_ape_event_lock()
831 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
834 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
865 return -ENODEV; in tg3_ape_scratchpad_read()
869 return -EAGAIN; in tg3_ape_scratchpad_read()
881 len -= length; in tg3_ape_scratchpad_read()
885 return -EAGAIN; in tg3_ape_scratchpad_read()
906 return -EAGAIN; in tg3_ape_scratchpad_read()
908 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
926 return -EAGAIN; in tg3_ape_send_event()
930 return -EAGAIN; in tg3_ape_send_event()
956 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
973 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
999 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
1002 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
1003 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1011 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1012 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1013 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1020 tp->irq_sync = 0; in tg3_enable_ints()
1024 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1026 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1027 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1028 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1030 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1032 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1034 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1039 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1040 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1042 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1044 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1049 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1050 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1055 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1060 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1064 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1065 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1078 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1080 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1088 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1089 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1106 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1134 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1136 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1140 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1162 loops -= 1; in __tg3_readphy()
1165 ret = -EBUSY; in __tg3_readphy()
1171 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1172 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1176 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1183 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1193 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1197 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1199 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1203 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1223 loops -= 1; in __tg3_writephy()
1226 ret = -EBUSY; in __tg3_writephy()
1230 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1231 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1235 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1242 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1372 return -EBUSY; in tg3_bmcr_reset()
1375 while (limit--) { in tg3_bmcr_reset()
1378 return -EBUSY; in tg3_bmcr_reset()
1387 return -EBUSY; in tg3_bmcr_reset()
1394 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1397 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1400 val = -EIO; in tg3_mdio_read()
1402 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1409 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1412 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1415 ret = -EIO; in tg3_mdio_write()
1417 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1427 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1428 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1446 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1505 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1506 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1523 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1531 tp->phy_addr += 7; in tg3_mdio_init()
1535 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1538 tp->phy_addr = addr; in tg3_mdio_init()
1540 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1547 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1548 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1549 return -ENOMEM; in tg3_mdio_init()
1551 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1552 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1553 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1554 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1555 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1556 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1557 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1558 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1568 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1570 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1571 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1575 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1577 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1578 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1579 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1580 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1581 return -ENODEV; in tg3_mdio_init()
1584 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1586 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1587 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1591 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1596 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; in tg3_mdio_init()
1598 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; in tg3_mdio_init()
1600 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; in tg3_mdio_init()
1603 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1607 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1608 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1609 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1625 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1626 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1630 /* tp->lock is held. */
1639 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1644 /* tp->lock is held. */
1652 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1653 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1667 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1674 /* tp->lock is held. */
1694 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1709 /* tp->lock is held. */
1731 /* tp->lock is held. */
1747 /* tp->lock is held. */
1776 /* tp->lock is held. */
1797 /* tp->lock is held. */
1841 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1842 return -ENODEV; in tg3_poll_fw()
1846 return -ENODEV; in tg3_poll_fw()
1854 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1857 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1874 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1889 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1890 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1893 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1894 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1896 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1898 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1901 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1902 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1904 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1907 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1908 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1909 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1914 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1981 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1982 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1985 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1987 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1990 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1995 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1997 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
2000 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2002 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2004 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
2005 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
2008 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2010 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2012 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
2013 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2021 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2023 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2025 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2028 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2030 if (phydev->link) { in tg3_adjust_link()
2034 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2036 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2042 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2046 tp->link_config.flowctrl); in tg3_adjust_link()
2048 if (phydev->pause) in tg3_adjust_link()
2050 if (phydev->asym_pause) in tg3_adjust_link()
2058 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2059 tp->mac_mode = mac_mode; in tg3_adjust_link()
2060 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2065 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2073 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2084 if (phydev->link != tp->old_link || in tg3_adjust_link()
2085 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2086 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2087 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2090 tp->old_link = phydev->link; in tg3_adjust_link()
2091 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2092 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2094 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2104 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2110 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2113 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2114 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2116 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2121 switch (phydev->interface) { in tg3_phy_init()
2124 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2125 phydev->supported &= (PHY_GBIT_FEATURES | in tg3_phy_init()
2132 phydev->supported &= (PHY_BASIC_FEATURES | in tg3_phy_init()
2137 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2138 return -EINVAL; in tg3_phy_init()
2141 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2143 phydev->advertising = phydev->supported; in tg3_phy_init()
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2157 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2159 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2160 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2161 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2162 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2163 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2164 phydev->advertising = tp->link_config.advertising; in tg3_phy_start()
2174 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2177 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2182 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2183 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2184 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2193 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2196 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2197 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2244 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2247 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2274 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2277 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2315 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2328 if (!tp->phy_otp) in tg3_phy_apply_otp()
2331 otp = tp->phy_otp; in tg3_phy_apply_otp()
2364 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2366 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2378 dest->eee_active = 1; in tg3_eee_pull_config()
2380 dest->eee_active = 0; in tg3_eee_pull_config()
2385 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2390 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2391 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2395 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2398 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2405 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2408 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2410 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2412 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2413 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2414 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2417 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2425 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2426 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2429 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2445 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2464 while (limit--) { in tg3_wait_macro_done()
2473 return -EBUSY; in tg3_wait_macro_done()
2502 return -EBUSY; in tg3_phy_write_and_check_testpat()
2510 return -EBUSY; in tg3_phy_write_and_check_testpat()
2516 return -EBUSY; in tg3_phy_write_and_check_testpat()
2526 return -EBUSY; in tg3_phy_write_and_check_testpat()
2536 return -EBUSY; in tg3_phy_write_and_check_testpat()
2558 return -EBUSY; in tg3_phy_reset_chanpat()
2586 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2607 } while (--retries); in tg3_phy_reset_5703_4_5()
2634 netif_carrier_off(tp->dev); in tg3_carrier_off()
2635 tp->link_up = false; in tg3_carrier_off()
2641 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2642 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2646 * link unless the FORCE argument is non-zero.
2661 return -EBUSY; in tg3_phy_reset()
2663 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2664 netif_carrier_off(tp->dev); in tg3_phy_reset()
2709 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2714 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2720 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2727 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2732 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2739 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2742 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2755 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2756 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2759 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2815 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2837 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2841 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2846 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2862 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2884 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2891 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2892 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2893 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2899 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2917 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2923 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2936 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2942 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2948 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2995 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2998 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3025 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3027 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3043 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3047 if (!tp->pci_fn) in tg3_phy_power_bug()
3052 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3053 !tp->pci_fn) in tg3_phy_power_bug()
3066 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3067 !tp->pci_fn) in tg3_phy_led_bug()
3079 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3082 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3101 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3149 /* tp->lock is held. */
3155 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3164 return -ENODEV; in tg3_nvram_lock()
3167 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3172 /* tp->lock is held. */
3176 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3177 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3178 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3183 /* tp->lock is held. */
3193 /* tp->lock is held. */
3210 return -EINVAL; in tg3_nvram_read_using_eeprom()
3230 return -EBUSY; in tg3_nvram_read_using_eeprom()
3259 return -EBUSY; in tg3_nvram_exec_cmd()
3270 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3272 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3274 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3285 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3288 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3289 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3298 * machine, the 32-bit value will be byteswapped.
3310 return -EINVAL; in tg3_nvram_read()
3383 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3396 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3397 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3403 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3425 len -= size; in tg3_nvram_write_block_unbuffered()
3429 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3471 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3503 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3511 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3514 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3524 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3551 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3588 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3600 /* tp->lock is held. */
3611 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3612 return -EBUSY; in tg3_pause_cpu()
3615 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3618 /* tp->lock is held. */
3630 /* tp->lock is held. */
3636 /* tp->lock is held. */
3643 /* tp->lock is held. */
3649 /* tp->lock is held. */
3676 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3678 return -ENODEV; in tg3_halt_cpu()
3696 * tp->fw->size minus headers. in tg3_fw_data_len()
3706 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3707 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3709 fw_len = tp->fw->size; in tg3_fw_data_len()
3711 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3714 /* tp->lock is held. */
3721 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3724 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3727 return -EINVAL; in tg3_load_firmware_cpu()
3755 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3763 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3767 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3771 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3780 /* tp->lock is held. */
3798 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3801 /* tp->lock is held. */
3807 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3811 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3829 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3831 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3834 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3835 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3860 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3861 return -EBUSY; in tg3_validate_rxcpu_state()
3866 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3868 return -EEXIST; in tg3_validate_rxcpu_state()
3874 /* tp->lock is held. */
3885 if (!tp->fw) in tg3_load_57766_firmware()
3890 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3902 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3903 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3915 /* tp->lock is held. */
3925 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3929 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3933 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3952 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3954 netdev_err(tp->dev, in tg3_load_tso_firmware()
3957 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3958 return -ENODEV; in tg3_load_tso_firmware()
3965 /* tp->lock is held. */
3978 index -= 4; in __tg3_set_one_mac_addr()
3984 /* tp->lock is held. */
3993 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3999 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
4002 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
4003 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
4004 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
4005 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
4006 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
4007 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
4018 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4019 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4028 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4033 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4050 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4057 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4062 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4063 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4067 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4069 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4071 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4072 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4073 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4074 tp->link_config.advertising = phydev->advertising; in tg3_power_down_prepare()
4091 phydev->advertising = advertising; in tg3_power_down_prepare()
4095 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4107 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4108 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4110 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4139 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4141 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4150 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4152 else if (tp->phy_flags & in tg3_power_down_prepare()
4154 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4161 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4175 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4199 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4226 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4229 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4245 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4281 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4282 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4319 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4345 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4357 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4368 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4371 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4375 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4377 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4379 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4418 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4419 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4422 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4423 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4429 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4430 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4438 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4439 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4443 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4448 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4449 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4463 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4464 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4475 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4489 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4523 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4524 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4527 err = -EIO; in tg3_phy_pull_config()
4531 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4537 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4540 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4543 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4544 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4553 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4555 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4557 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4563 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4564 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4575 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4577 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4579 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4582 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4585 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4597 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4603 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4633 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4638 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4639 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4640 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4641 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4656 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4660 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4661 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4671 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4700 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4713 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4720 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4722 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4724 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4725 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4726 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4763 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4773 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4777 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4795 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4797 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4803 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4809 tp->link_up) { in tg3_setup_copper_phy()
4818 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4839 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4842 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4863 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4865 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4870 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4880 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4881 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4883 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4932 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4933 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4935 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4949 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4956 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4957 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4963 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4966 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4975 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4982 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4990 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4991 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4996 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
5000 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
5002 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5003 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5004 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5006 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5007 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
5008 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5010 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5019 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5021 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5024 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5032 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5033 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5034 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5038 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5039 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5041 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5047 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5049 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5050 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5054 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5069 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5083 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5084 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5085 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5088 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5157 #define ANEG_FAILED -1
5169 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5170 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5171 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5172 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5173 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5174 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5175 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5176 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5177 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5179 ap->cur_time++; in tg3_fiber_aneg_smachine()
5184 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5185 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5186 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5187 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5189 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5190 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5191 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5195 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5197 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5199 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5201 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5202 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5203 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5204 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5205 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5210 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5213 switch (ap->state) { in tg3_fiber_aneg_smachine()
5215 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5216 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5220 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5221 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5222 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5223 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5224 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5225 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5226 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5227 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5228 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5230 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5232 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5237 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5238 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5239 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5241 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5242 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5246 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5250 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5252 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5262 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5263 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5264 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5266 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5268 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5269 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5270 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5271 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5274 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5278 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5279 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5283 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5284 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5285 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5286 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5289 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5293 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5294 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5295 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5296 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5298 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5300 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5301 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5302 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5307 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5311 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5322 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5323 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5324 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5325 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5326 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5327 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5328 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5329 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5330 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5331 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5332 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5333 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5335 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5337 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5338 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5339 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5340 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5341 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5342 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5344 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5349 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5350 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5351 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5354 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5356 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5357 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5359 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5360 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5361 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5370 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5371 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5372 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5375 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5380 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5381 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5382 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5385 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5388 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5393 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5423 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5427 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5443 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5444 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5482 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5528 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5529 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5535 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5556 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5559 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5566 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5567 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5571 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5582 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5583 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5603 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5608 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5609 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5611 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5612 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5628 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5636 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5638 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5645 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5646 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5660 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5677 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5707 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5710 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5727 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5728 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5729 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5732 tp->link_up && in tg3_setup_fiber_phy()
5749 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5750 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5751 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5754 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5762 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5770 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5772 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5787 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5788 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5789 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5792 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5797 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5798 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5799 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5803 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5804 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5805 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5811 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5813 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5814 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5838 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5841 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5846 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5849 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5852 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5861 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5869 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5870 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5878 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5891 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5892 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5894 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5903 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5904 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5912 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5913 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5923 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5933 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5957 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5985 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5999 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
6000 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
6001 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
6003 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
6008 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
6009 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6017 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6019 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6023 if (!tp->link_up && in tg3_serdes_parallel_detect()
6024 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6029 u32 phy1, phy2; in tg3_serdes_parallel_detect() local
6033 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6041 if ((phy1 & 0x10) && !(phy2 & 0x20)) { in tg3_serdes_parallel_detect()
6050 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6053 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6054 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6055 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6069 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6080 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6082 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6111 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6112 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6120 if (tp->link_up) { in tg3_setup_phy()
6122 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6130 if (!tp->link_up) in tg3_setup_phy()
6132 tp->pwrmgmt_thresh; in tg3_setup_phy()
6141 /* tp->lock must be held */
6148 /* tp->lock must be held */
6165 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6170 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6175 if (tp->ptp_clock) in tg3_get_ts_info()
6176 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6178 info->phc_index = -1; in tg3_get_ts_info()
6180 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6182 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6197 ppb = -ppb; in tg3_ptp_adjfreq()
6230 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6243 ns += tp->ptp_adjust; in tg3_ptp_gettime()
6261 tp->ptp_adjust = 0; in tg3_ptp_settime()
6274 switch (rq->type) { in tg3_ptp_enable()
6276 if (rq->perout.index != 0) in tg3_ptp_enable()
6277 return -EINVAL; in tg3_ptp_enable()
6286 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6287 rq->perout.start.nsec; in tg3_ptp_enable()
6289 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6290 netdev_warn(tp->dev, in tg3_ptp_enable()
6291 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6292 rval = -EINVAL; in tg3_ptp_enable()
6297 netdev_warn(tp->dev, in tg3_ptp_enable()
6299 rval = -EINVAL; in tg3_ptp_enable()
6323 return -EOPNOTSUPP; in tg3_ptp_enable()
6346 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6347 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6350 /* tp->lock must be held */
6358 tp->ptp_adjust = 0; in tg3_ptp_init()
6359 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6362 /* tp->lock must be held */
6368 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6369 tp->ptp_adjust = 0; in tg3_ptp_resume()
6374 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6377 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6378 tp->ptp_clock = NULL; in tg3_ptp_fini()
6379 tp->ptp_adjust = 0; in tg3_ptp_fini()
6384 return tp->irq_sync; in tg3_irq_sync()
6467 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6474 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6475 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6478 netdev_err(tp->dev, in tg3_dump_state()
6481 tnapi->hw_status->status, in tg3_dump_state()
6482 tnapi->hw_status->status_tag, in tg3_dump_state()
6483 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6484 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6485 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6486 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6487 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6489 netdev_err(tp->dev, in tg3_dump_state()
6492 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6493 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6494 tnapi->rx_rcb_ptr, in tg3_dump_state()
6495 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6496 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6497 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6498 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6502 /* This is called whenever we suspect that the system chipset is re-
6511 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6513 netdev_warn(tp->dev, in tg3_tx_recover()
6514 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6526 return tnapi->tx_pending - in tg3_tx_avail()
6527 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6536 struct tg3 *tp = tnapi->tp; in tg3_tx()
6537 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6538 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6540 int index = tnapi - tp->napi; in tg3_tx()
6544 index--; in tg3_tx()
6546 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6549 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6550 struct sk_buff *skb = ri->skb; in tg3_tx()
6558 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6568 pci_unmap_single(tp->pdev, in tg3_tx()
6573 ri->skb = NULL; in tg3_tx()
6575 while (ri->fragmented) { in tg3_tx()
6576 ri->fragmented = false; in tg3_tx()
6578 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6583 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6584 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6585 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6588 pci_unmap_page(tp->pdev, in tg3_tx()
6590 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6593 while (ri->fragmented) { in tg3_tx()
6594 ri->fragmented = false; in tg3_tx()
6596 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6603 bytes_compl += skb->len; in tg3_tx()
6615 tnapi->tx_cons = sw_idx; in tg3_tx()
6647 if (!ri->data) in tg3_rx_data_free()
6650 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), in tg3_rx_data_free()
6652 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6653 ri->data = NULL; in tg3_rx_data_free()
6680 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6681 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6682 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6683 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6687 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6688 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6689 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6694 return -EINVAL; in tg3_alloc_rx_data()
6713 return -ENOMEM; in tg3_alloc_rx_data()
6715 mapping = pci_map_single(tp->pdev, in tg3_alloc_rx_data()
6719 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { in tg3_alloc_rx_data()
6721 return -EIO; in tg3_alloc_rx_data()
6724 map->data = data; in tg3_alloc_rx_data()
6727 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6728 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6742 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6745 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6750 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6751 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6752 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6753 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6754 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6758 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6759 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6760 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6761 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6762 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6769 dest_map->data = src_map->data; in tg3_recycle_rx()
6772 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6773 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6780 src_map->data = NULL; in tg3_recycle_rx()
6795 * it is first placed into the on-chip ram. When the packet's length
6803 * rings, then cache lines never move beyond shared-modified state.
6809 struct tg3 *tp = tnapi->tp; in tg3_rx()
6812 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6815 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6817 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6825 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6826 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6829 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6837 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6838 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6840 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6842 data = ri->data; in tg3_rx()
6846 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6848 data = ri->data; in tg3_rx()
6855 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6861 tp->rx_dropped++; in tg3_rx()
6866 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6869 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6871 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6886 pci_unmap_single(tp->pdev, dma_addr, skb_size, in tg3_rx()
6894 ri->data = NULL; in tg3_rx()
6906 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6912 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6913 memcpy(skb->data, in tg3_rx()
6916 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6924 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6925 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6926 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6928 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6932 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6934 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6935 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6936 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6941 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6942 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6944 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6946 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6949 budget--; in tg3_rx()
6954 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6955 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6956 tp->rx_std_ring_mask; in tg3_rx()
6958 tpr->rx_std_prod_idx); in tg3_rx()
6964 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6968 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6974 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
6975 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
6983 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6984 tp->rx_std_ring_mask; in tg3_rx()
6986 tpr->rx_std_prod_idx); in tg3_rx()
6989 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
6990 tp->rx_jmb_ring_mask; in tg3_rx()
6992 tpr->rx_jmb_prod_idx); in tg3_rx()
7001 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7002 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7004 if (tnapi != &tp->napi[1]) { in tg3_rx()
7005 tp->rx_refill = true; in tg3_rx()
7006 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7017 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7019 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7020 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7021 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7022 spin_lock(&tp->lock); in tg3_poll_link()
7032 spin_unlock(&tp->lock); in tg3_poll_link()
7045 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7052 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7055 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7056 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7058 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7059 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7062 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7064 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7065 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7068 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7069 cpycnt = i - di; in tg3_rx_prodring_xfer()
7070 err = -ENOSPC; in tg3_rx_prodring_xfer()
7084 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7085 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7090 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7091 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7092 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7093 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7096 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7097 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7098 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7099 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7103 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7110 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7113 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7114 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7116 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7117 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7120 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7122 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7123 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7126 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7127 cpycnt = i - di; in tg3_rx_prodring_xfer()
7128 err = -ENOSPC; in tg3_rx_prodring_xfer()
7142 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7143 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7148 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7149 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7150 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7151 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7154 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7155 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7156 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7157 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7165 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7168 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7174 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7179 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7181 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7182 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7184 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7185 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7187 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7188 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7190 tp->rx_refill = false; in tg3_poll_work()
7191 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7193 &tp->napi[i].prodring); in tg3_poll_work()
7197 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7199 dpr->rx_std_prod_idx); in tg3_poll_work()
7201 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7203 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7208 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7216 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7217 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7222 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7223 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7230 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7232 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7243 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7247 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7248 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7252 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7253 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7258 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7263 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7268 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7269 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7271 tnapi->coal_now); in tg3_poll_msix()
7299 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7304 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7309 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7325 struct tg3 *tp = tnapi->tp; in tg3_poll()
7327 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7330 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7344 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7348 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7349 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7352 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7375 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7376 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7383 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7384 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7391 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); in tg3_napi_init()
7392 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7393 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); in tg3_napi_init()
7400 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7401 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7406 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7408 netif_carrier_off(tp->dev); in tg3_netif_stop()
7409 netif_tx_disable(tp->dev); in tg3_netif_stop()
7412 /* tp->lock must be held */
7421 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7423 if (tp->link_up) in tg3_netif_start()
7424 netif_carrier_on(tp->dev); in tg3_netif_start()
7427 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7432 __releases(tp->lock) in tg3_irq_quiesce()
7433 __acquires(tp->lock) in tg3_irq_quiesce()
7437 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7439 tp->irq_sync = 1; in tg3_irq_quiesce()
7442 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7444 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7445 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7447 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7451 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7457 spin_lock_bh(&tp->lock); in tg3_full_lock()
7464 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7467 /* One-shot MSI handler - Chip automatically disables interrupt
7473 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7475 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7476 if (tnapi->rx_rcb) in tg3_msi_1shot()
7477 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7480 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7485 /* MSI ISR - No need to check for interrupt sharing and no need to
7492 struct tg3 *tp = tnapi->tp; in tg3_msi()
7494 prefetch(tnapi->hw_status); in tg3_msi()
7495 if (tnapi->rx_rcb) in tg3_msi()
7496 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7498 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7499 * chip-internal interrupt pending events. in tg3_msi()
7500 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7501 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7504 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7506 napi_schedule(&tnapi->napi); in tg3_msi()
7514 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7515 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7523 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7532 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7533 * chip-internal interrupt pending events. in tg3_interrupt()
7534 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7535 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7538 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7545 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7547 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7548 napi_schedule(&tnapi->napi); in tg3_interrupt()
7550 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7563 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7564 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7572 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7581 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7582 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7583 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7584 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7587 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7599 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7604 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7606 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7616 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7617 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7619 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7636 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7637 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7675 /* Test for DMA addresses > 40-bit */
7692 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7693 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7694 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7695 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7702 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7717 if (tp->dma_limit) { in tg3_tx_frag_set()
7720 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7721 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7722 len -= tp->dma_limit; in tg3_tx_frag_set()
7726 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7727 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7730 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7732 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7734 *budget -= 1; in tg3_tx_frag_set()
7743 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7745 *budget -= 1; in tg3_tx_frag_set()
7749 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7753 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7765 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7767 skb = txb->skb; in tg3_tx_skb_unmap()
7768 txb->skb = NULL; in tg3_tx_skb_unmap()
7770 pci_unmap_single(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7775 while (txb->fragmented) { in tg3_tx_skb_unmap()
7776 txb->fragmented = false; in tg3_tx_skb_unmap()
7778 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7782 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7785 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7787 pci_unmap_page(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7791 while (txb->fragmented) { in tg3_tx_skb_unmap()
7792 txb->fragmented = false; in tg3_tx_skb_unmap()
7794 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7799 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7805 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7813 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7821 ret = -1; in tigon3_dma_hwbug_workaround()
7824 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, in tigon3_dma_hwbug_workaround()
7827 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
7829 ret = -1; in tigon3_dma_hwbug_workaround()
7835 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7836 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7840 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7842 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7844 ret = -1; in tigon3_dma_hwbug_workaround()
7859 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7871 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7889 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7896 segs = segs->next; in tg3_tso_bug()
7897 nskb->next = NULL; in tg3_tso_bug()
7898 tg3_start_xmit(nskb, tp->dev); in tg3_tso_bug()
7913 int i = -1, would_hit_hwbug; in tg3_start_xmit()
7924 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7931 * and TX reclaim runs via tp->napi.poll inside of a software in tg3_start_xmit()
7935 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
7946 entry = tnapi->tx_prod; in tg3_start_xmit()
7949 mss = skb_shinfo(skb)->gso_size; in tg3_start_xmit()
7959 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN; in tg3_start_xmit()
7964 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
7965 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
7978 ip_csum = iph->check; in tg3_start_xmit()
7979 ip_tot_len = iph->tot_len; in tg3_start_xmit()
7980 iph->check = 0; in tg3_start_xmit()
7981 iph->tot_len = htons(mss + hdr_len); in tg3_start_xmit()
7988 tcp_csum = tcph->check; in tg3_start_xmit()
7993 tcph->check = 0; in tg3_start_xmit()
7996 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in tg3_start_xmit()
8009 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8012 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8016 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8019 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8023 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in tg3_start_xmit()
8027 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
8028 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
8037 !mss && skb->len > VLAN_ETH_FRAME_LEN) in tg3_start_xmit()
8045 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in tg3_start_xmit()
8047 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in tg3_start_xmit()
8053 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); in tg3_start_xmit()
8054 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
8058 tnapi->tx_buffers[entry].skb = skb; in tg3_start_xmit()
8059 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in tg3_start_xmit()
8067 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in tg3_start_xmit()
8070 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
8081 last = skb_shinfo(skb)->nr_frags - 1; in tg3_start_xmit()
8083 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_start_xmit()
8086 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8089 tnapi->tx_buffers[entry].skb = NULL; in tg3_start_xmit()
8090 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in tg3_start_xmit()
8092 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8107 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in tg3_start_xmit()
8114 iph->check = ip_csum; in tg3_start_xmit()
8115 iph->tot_len = ip_tot_len; in tg3_start_xmit()
8117 tcph->check = tcp_csum; in tg3_start_xmit()
8124 entry = tnapi->tx_prod; in tg3_start_xmit()
8132 netdev_tx_sent_queue(txq, skb->len); in tg3_start_xmit()
8137 tnapi->tx_prod = entry; in tg3_start_xmit()
8151 if (!skb->xmit_more || netif_xmit_stopped(txq)) { in tg3_start_xmit()
8153 tw32_tx_mbox(tnapi->prodmbox, entry); in tg3_start_xmit()
8160 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in tg3_start_xmit()
8161 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in tg3_start_xmit()
8165 tp->tx_dropped++; in tg3_start_xmit()
8172 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8175 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8178 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8180 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8181 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8183 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8185 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8188 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8190 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8193 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8205 return -EIO; in tg3_phy_lpbk_set()
8216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8226 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8242 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8247 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8258 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8262 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8265 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8273 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8295 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8298 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8300 netif_carrier_on(tp->dev); in tg3_set_loopback()
8301 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8304 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8307 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8311 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8321 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8329 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8342 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8343 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8344 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8345 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8346 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8349 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8350 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8351 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8352 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8360 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8361 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8362 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8365 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8366 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8375 * end up in the driver. tp->{tx,}lock are held and thus
8383 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8384 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8385 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8386 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8388 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8389 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8391 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8392 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8398 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8402 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8404 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8410 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8413 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8414 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8416 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8421 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8426 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8429 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8432 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8440 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8445 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8448 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8449 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8450 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8452 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8456 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8461 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8464 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8467 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8477 return -ENOMEM; in tg3_rx_prodring_alloc()
8483 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8484 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8485 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8486 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8487 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8488 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8489 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8490 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8492 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8493 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8494 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8495 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8502 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8504 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8505 return -ENOMEM; in tg3_rx_prodring_init()
8507 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8509 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8511 if (!tpr->rx_std) in tg3_rx_prodring_init()
8515 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8517 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8520 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8522 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8524 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8532 return -ENOMEM; in tg3_rx_prodring_init()
8539 * end up in the driver. tp->{tx,}lock is not held and we are not
8546 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8547 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8549 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8551 if (!tnapi->tx_buffers) in tg3_free_rings()
8555 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8561 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8565 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8573 * end up in the driver. tp->{tx,}lock are held and thus
8583 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8584 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8586 tnapi->last_tag = 0; in tg3_init_rings()
8587 tnapi->last_irq_tag = 0; in tg3_init_rings()
8588 tnapi->hw_status->status = 0; in tg3_init_rings()
8589 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8592 tnapi->tx_prod = 0; in tg3_init_rings()
8593 tnapi->tx_cons = 0; in tg3_init_rings()
8594 if (tnapi->tx_ring) in tg3_init_rings()
8595 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8597 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8598 if (tnapi->rx_rcb) in tg3_init_rings()
8599 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8601 if (tnapi->prodring.rx_std && in tg3_init_rings()
8602 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8604 return -ENOMEM; in tg3_init_rings()
8615 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8616 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8618 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8619 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8620 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8621 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8624 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8625 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8632 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8640 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8641 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8644 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8647 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8649 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8651 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8659 return -ENOMEM; in tg3_mem_tx_acquire()
8666 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8667 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8669 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8671 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8674 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8676 tnapi->rx_rcb, in tg3_mem_rx_release()
8677 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8678 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8686 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8695 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8697 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8707 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8709 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8711 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8719 return -ENOMEM; in tg3_mem_rx_acquire()
8730 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8731 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8733 if (tnapi->hw_status) { in tg3_free_consistent()
8734 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8735 tnapi->hw_status, in tg3_free_consistent()
8736 tnapi->status_mapping); in tg3_free_consistent()
8737 tnapi->hw_status = NULL; in tg3_free_consistent()
8744 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8746 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8748 if (tp->hw_stats) { in tg3_free_consistent()
8749 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8750 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8751 tp->hw_stats = NULL; in tg3_free_consistent()
8763 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8765 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8766 if (!tp->hw_stats) in tg3_alloc_consistent()
8769 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8770 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8773 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8775 &tnapi->status_mapping, in tg3_alloc_consistent()
8777 if (!tnapi->hw_status) in tg3_alloc_consistent()
8780 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8793 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8796 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8799 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8802 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8805 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8807 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8818 return -ENOMEM; in tg3_alloc_consistent()
8824 * clears. tp->lock is held.
8853 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8854 dev_err(&tp->pdev->dev, in tg3_stop_block()
8858 return -ENODEV; in tg3_stop_block()
8868 dev_err(&tp->pdev->dev, in tg3_stop_block()
8871 return -ENODEV; in tg3_stop_block()
8877 /* tp->lock is held. */
8884 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8885 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8886 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8887 err = -ENODEV; in tg3_abort_hw()
8891 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8892 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8910 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8911 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8914 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8915 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8923 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8926 err |= -ENODEV; in tg3_abort_hw()
8940 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8941 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8942 if (tnapi->hw_status) in tg3_abort_hw()
8943 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
8952 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8960 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
8961 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8962 tp->misc_host_ctrl); in tg3_restore_pci_state()
8974 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8976 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8979 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8980 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8981 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8982 tp->pci_lat_timer); in tg3_restore_pci_state()
8985 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
8989 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8992 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9004 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9005 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9007 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9008 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9059 /* tp->lock is held. */
9061 __releases(tp->lock) in tg3_chip_reset()
9062 __acquires(tp->lock) in tg3_chip_reset()
9068 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9069 return -ENODEV; in tg3_chip_reset()
9078 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9096 write_op = tp->write32; in tg3_chip_reset()
9098 tp->write32 = tg3_write32; in tg3_chip_reset()
9107 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9108 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9109 if (tnapi->hw_status) { in tg3_chip_reset()
9110 tnapi->hw_status->status = 0; in tg3_chip_reset()
9111 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9113 tnapi->last_tag = 0; in tg3_chip_reset()
9114 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9120 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9121 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9167 tp->write32 = write_op; in tg3_chip_reset()
9190 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9194 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9205 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9206 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9218 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9221 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9257 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9265 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9267 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9269 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9270 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9273 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9274 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9275 val = tp->mac_mode; in tg3_chip_reset()
9276 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9277 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9278 val = tp->mac_mode; in tg3_chip_reset()
9311 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9322 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9328 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9330 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9341 /* tp->lock is held. */
9358 if (tp->hw_stats) { in tg3_halt()
9360 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9361 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9364 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9377 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9378 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9380 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); in tg3_set_mac_addr()
9398 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9401 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9406 /* tp->lock is held. */
9433 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9434 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9435 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9441 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9445 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9447 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9449 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9453 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9463 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9466 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9467 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9468 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9469 limit--; in tg3_coal_rx_init()
9480 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9482 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9484 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9487 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9500 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9502 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9503 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9505 if (!tp->link_up) in __tg3_set_coalesce()
9512 /* tp->lock is held. */
9534 /* tp->lock is held. */
9543 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9544 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9546 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9549 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9555 /* tp->lock is held. */
9578 /* tp->lock is held. */
9587 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9588 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9590 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9593 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9594 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9599 /* tp->lock is held. */
9604 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9611 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9612 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9613 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9614 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9618 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9619 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9620 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9622 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9623 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9624 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9625 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9626 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9627 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9630 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9632 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9633 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9634 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9635 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9638 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9646 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9650 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9652 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9656 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9657 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9663 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9686 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9687 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9700 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9747 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9758 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9761 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9776 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9791 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9797 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9803 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9804 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9815 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9825 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9826 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9832 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9837 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9846 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9850 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9865 /* tp->lock is held. */
9870 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9881 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9882 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9885 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10003 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10004 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10050 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10056 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10059 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10063 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10065 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10066 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10068 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10071 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10074 if (tp->rxptpctl) in tg3_reset_hw()
10076 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10081 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10087 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10088 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10113 fw_len = tp->fw_len; in tg3_reset_hw()
10114 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10118 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10121 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10123 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10125 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10127 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10130 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10132 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10134 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10137 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10139 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10156 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10157 return -ENODEV; in tg3_reset_hw()
10183 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10185 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10203 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10205 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10231 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10232 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10234 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10235 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10236 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10245 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10300 tp->dma_limit = 0; in tg3_reset_hw()
10301 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10303 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10389 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10397 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10399 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10413 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10420 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10421 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10427 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10431 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10433 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10435 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10436 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10439 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10459 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10464 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10467 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10473 if (tp->irq_cnt > 1) in tg3_reset_hw()
10516 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10525 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10592 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10596 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10601 tp->tx_mode &= ~val; in tg3_reset_hw()
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10605 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10619 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10621 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10624 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10627 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10634 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10637 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10640 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10644 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10647 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10649 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10651 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10671 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10672 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10676 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10682 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10683 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10684 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10689 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10696 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10708 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10721 limit -= 4; in tg3_reset_hw()
10781 * packet processing. Invoked with tp->lock held.
10810 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10811 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10824 spin_lock_bh(&tp->lock); in tg3_show_temp()
10825 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10827 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10849 if (tp->hwmon_dev) { in tg3_hwmon_close()
10850 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10851 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10859 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10875 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10877 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10878 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10879 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10890 (PSTAT)->low += __val; \
10891 if ((PSTAT)->low < __val) \
10892 (PSTAT)->high += 1; \
10897 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10899 if (!tp->link_up) in tg3_periodic_fetch_stats()
10902 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10903 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10904 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10905 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10906 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10907 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10908 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10909 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10910 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10911 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10912 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10913 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10914 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10916 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10917 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
10926 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10927 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
10928 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
10929 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
10930 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
10931 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
10932 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
10933 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10934 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10935 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
10936 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
10937 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
10938 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
10939 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
10941 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
10946 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
10952 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
10953 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
10954 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
10956 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
10958 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
10965 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10966 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10969 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
10970 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
10971 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
10972 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
10978 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
10979 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
10980 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
10988 spin_lock(&tp->lock); in tg3_timer()
10990 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10991 spin_unlock(&tp->lock); in tg3_timer()
11005 /* All of this garbage is because when using non-tagged in tg3_timer()
11009 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11011 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11013 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11018 spin_unlock(&tp->lock); in tg3_timer()
11025 if (!--tp->timer_counter) { in tg3_timer()
11029 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11039 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11051 if (tp->link_up && in tg3_timer()
11055 if (!tp->link_up && in tg3_timer()
11061 if (!tp->serdes_counter) { in tg3_timer()
11063 (tp->mac_mode & in tg3_timer()
11066 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11071 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11079 if (link_up != tp->link_up) in tg3_timer()
11083 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11103 if (!--tp->asf_counter) { in tg3_timer()
11115 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11121 spin_unlock(&tp->lock); in tg3_timer()
11124 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11125 add_timer(&tp->timer); in tg3_timer()
11133 tp->timer_offset = HZ; in tg3_timer_init()
11135 tp->timer_offset = HZ / 10; in tg3_timer_init()
11137 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11139 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11140 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11143 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11148 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11149 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11151 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11152 add_timer(&tp->timer); in tg3_timer_start()
11157 del_timer_sync(&tp->timer); in tg3_timer_stop()
11160 /* Restart hardware after configuration changes, self-test, etc.
11161 * Invoked with tp->lock held.
11164 __releases(tp->lock) in tg3_restart_hw()
11165 __acquires(tp->lock) in tg3_restart_hw()
11171 netdev_err(tp->dev, in tg3_restart_hw()
11172 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11176 tp->irq_sync = 0; in tg3_restart_hw()
11178 dev_close(tp->dev); in tg3_restart_hw()
11192 if (!netif_running(tp->dev)) { in tg3_reset_task()
11208 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11209 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11218 tp->irq_sync = 0; in tg3_reset_task()
11224 dev_close(tp->dev); in tg3_reset_task()
11245 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11247 if (tp->irq_cnt == 1) in tg3_request_irq()
11248 name = tp->dev->name; in tg3_request_irq()
11250 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11251 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11253 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11254 else if (tnapi->tx_buffers) in tg3_request_irq()
11256 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11257 else if (tnapi->rx_rcb) in tg3_request_irq()
11259 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11262 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11263 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11278 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11283 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11284 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11289 return -ENODEV; in tg3_test_interrupt()
11293 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11304 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11305 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11309 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11312 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11313 tnapi->coal_now); in tg3_test_interrupt()
11318 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11328 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11329 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11336 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11352 return -EIO; in tg3_test_interrupt()
11369 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11370 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11375 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11381 if (err != -EIO) in tg3_test_msi()
11385 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11389 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11391 pci_disable_msi(tp->pdev); in tg3_test_msi()
11394 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11411 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11420 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11421 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11422 tp->fw_needed); in tg3_request_firmware()
11423 return -ENOENT; in tg3_request_firmware()
11426 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11433 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11434 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11435 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11436 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11437 release_firmware(tp->fw); in tg3_request_firmware()
11438 tp->fw = NULL; in tg3_request_firmware()
11439 return -EINVAL; in tg3_request_firmware()
11443 tp->fw_needed = NULL; in tg3_request_firmware()
11449 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11453 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11457 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11468 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11469 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11470 if (!tp->rxq_cnt) in tg3_enable_msix()
11471 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11472 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11473 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11475 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11479 if (!tp->txq_req) in tg3_enable_msix()
11480 tp->txq_cnt = 1; in tg3_enable_msix()
11482 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11484 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11489 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11492 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11493 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11494 tp->irq_cnt, rc); in tg3_enable_msix()
11495 tp->irq_cnt = rc; in tg3_enable_msix()
11496 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11497 if (tp->txq_cnt) in tg3_enable_msix()
11498 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11501 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11502 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11504 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11505 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11509 if (tp->irq_cnt == 1) in tg3_enable_msix()
11514 if (tp->txq_cnt > 1) in tg3_enable_msix()
11517 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11529 netdev_warn(tp->dev, in tg3_ints_init()
11536 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11541 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11549 tp->irq_cnt = 1; in tg3_ints_init()
11550 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11553 if (tp->irq_cnt == 1) { in tg3_ints_init()
11554 tp->txq_cnt = 1; in tg3_ints_init()
11555 tp->rxq_cnt = 1; in tg3_ints_init()
11556 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11557 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11564 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11566 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11576 struct net_device *dev = tp->dev; in tg3_start()
11598 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11601 for (i--; i >= 0; i--) { in tg3_start()
11602 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11604 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11666 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11667 tg3_set_loopback(dev, dev->features); in tg3_start()
11672 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11673 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11674 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11711 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11712 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11713 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11728 if (tp->pcierr_recovery) { in tg3_open()
11731 return -EAGAIN; in tg3_open()
11734 if (tp->fw_needed) { in tg3_open()
11738 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11739 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11740 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11741 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11742 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11748 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11751 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11770 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11774 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11784 if (tp->pcierr_recovery) { in tg3_close()
11787 return -EAGAIN; in tg3_close()
11792 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11802 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11807 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11809 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11821 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11823 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11826 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11830 estats->member = old_estats->member + \
11831 get_stat64(&hw_stats->member)
11835 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11836 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11919 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11920 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11922 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
11923 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
11924 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
11925 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
11927 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
11928 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
11929 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
11930 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
11932 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
11933 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
11934 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
11935 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
11937 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
11938 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
11939 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
11940 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
11941 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
11942 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
11943 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11945 stats->multicast = old_stats->multicast + in tg3_get_nstats()
11946 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
11947 stats->collisions = old_stats->collisions + in tg3_get_nstats()
11948 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
11950 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
11951 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
11952 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
11954 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
11955 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
11956 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
11957 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11958 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
11959 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
11961 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
11964 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
11965 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
11967 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11968 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11981 regs->version = 0; in tg3_get_regs()
11985 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11999 return tp->nvram_size; in tg3_get_eeprom_len()
12011 return -EINVAL; in tg3_get_eeprom()
12013 offset = eeprom->offset; in tg3_get_eeprom()
12014 len = eeprom->len; in tg3_get_eeprom()
12015 eeprom->len = 0; in tg3_get_eeprom()
12017 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12035 b_count = 4 - b_offset; in tg3_get_eeprom()
12040 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12044 len -= b_count; in tg3_get_eeprom()
12046 eeprom->len += b_count; in tg3_get_eeprom()
12050 pd = &data[eeprom->len]; in tg3_get_eeprom()
12051 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12055 i -= 4; in tg3_get_eeprom()
12056 eeprom->len += i; in tg3_get_eeprom()
12062 eeprom->len += i; in tg3_get_eeprom()
12063 ret = -EINTR; in tg3_get_eeprom()
12069 eeprom->len += i; in tg3_get_eeprom()
12073 pd = &data[eeprom->len]; in tg3_get_eeprom()
12075 b_offset = offset + len - b_count; in tg3_get_eeprom()
12080 eeprom->len += b_count; in tg3_get_eeprom()
12102 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12103 return -EINVAL; in tg3_set_eeprom()
12105 offset = eeprom->offset; in tg3_set_eeprom()
12106 len = eeprom->len; in tg3_set_eeprom()
12110 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12124 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12133 return -ENOMEM; in tg3_set_eeprom()
12137 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12138 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12157 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12158 return -EAGAIN; in tg3_get_link_ksettings()
12159 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12167 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12171 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12177 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12180 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12182 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12185 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12187 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12188 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12194 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12198 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12201 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12202 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12203 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12205 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12206 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12208 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12209 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12210 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12212 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12215 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12216 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12217 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12219 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12220 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12228 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12233 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12234 return -EAGAIN; in tg3_set_link_ksettings()
12235 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12239 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12240 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12241 return -EINVAL; in tg3_set_link_ksettings()
12243 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12244 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12245 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12246 return -EINVAL; in tg3_set_link_ksettings()
12249 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12251 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12256 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12260 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12270 return -EINVAL; in tg3_set_link_ksettings()
12281 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12283 return -EINVAL; in tg3_set_link_ksettings()
12285 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12286 return -EINVAL; in tg3_set_link_ksettings()
12290 return -EINVAL; in tg3_set_link_ksettings()
12296 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12297 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12298 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12300 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12301 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12303 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12304 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12305 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12308 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12324 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12325 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); in tg3_get_drvinfo()
12326 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12327 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12334 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12335 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12337 wol->supported = 0; in tg3_get_wol()
12338 wol->wolopts = 0; in tg3_get_wol()
12339 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12340 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12341 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12347 struct device *dp = &tp->pdev->dev; in tg3_set_wol() local
12349 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12350 return -EINVAL; in tg3_set_wol()
12351 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12352 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12353 return -EINVAL; in tg3_set_wol()
12355 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12357 if (device_may_wakeup(dp)) in tg3_set_wol()
12368 return tp->msg_enable; in tg3_get_msglevel()
12374 tp->msg_enable = value; in tg3_set_msglevel()
12383 return -EAGAIN; in tg3_nway_reset()
12385 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12386 return -EINVAL; in tg3_nway_reset()
12391 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12392 return -EAGAIN; in tg3_nway_reset()
12393 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12397 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12398 r = -EINVAL; in tg3_nway_reset()
12402 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12407 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12417 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12419 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12421 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12423 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12425 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12427 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12429 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12431 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12440 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12441 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12442 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12443 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12445 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12446 return -EINVAL; in tg3_set_ringparam()
12456 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12459 tp->rx_pending > 63) in tg3_set_ringparam()
12460 tp->rx_pending = 63; in tg3_set_ringparam()
12463 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12465 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12466 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12493 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12495 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12496 epause->rx_pause = 1; in tg3_get_pauseparam()
12498 epause->rx_pause = 0; in tg3_get_pauseparam()
12500 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12501 epause->tx_pause = 1; in tg3_get_pauseparam()
12503 epause->tx_pause = 0; in tg3_get_pauseparam()
12512 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12519 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12521 if (!(phydev->supported & SUPPORTED_Pause) || in tg3_set_pauseparam()
12522 (!(phydev->supported & SUPPORTED_Asym_Pause) && in tg3_set_pauseparam()
12523 (epause->rx_pause != epause->tx_pause))) in tg3_set_pauseparam()
12524 return -EINVAL; in tg3_set_pauseparam()
12526 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12527 if (epause->rx_pause) { in tg3_set_pauseparam()
12528 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12530 if (epause->tx_pause) { in tg3_set_pauseparam()
12531 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12536 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12537 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12542 if (epause->autoneg) in tg3_set_pauseparam()
12547 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12548 u32 oldadv = phydev->advertising & in tg3_set_pauseparam()
12551 phydev->advertising &= in tg3_set_pauseparam()
12554 phydev->advertising |= newadv; in tg3_set_pauseparam()
12555 if (phydev->autoneg) { in tg3_set_pauseparam()
12568 if (!epause->autoneg) in tg3_set_pauseparam()
12571 tp->link_config.advertising &= in tg3_set_pauseparam()
12574 tp->link_config.advertising |= newadv; in tg3_set_pauseparam()
12586 if (epause->autoneg) in tg3_set_pauseparam()
12590 if (epause->rx_pause) in tg3_set_pauseparam()
12591 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12593 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12594 if (epause->tx_pause) in tg3_set_pauseparam()
12595 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12597 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12615 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12628 return -EOPNOTSUPP; in tg3_get_sset_count()
12638 return -EOPNOTSUPP; in tg3_get_rxnfc()
12640 switch (info->cmd) { in tg3_get_rxnfc()
12642 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12643 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12645 info->data = num_online_cpus(); in tg3_get_rxnfc()
12646 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12647 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12653 return -EOPNOTSUPP; in tg3_get_rxnfc()
12679 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12695 return -EOPNOTSUPP; in tg3_set_rxfh()
12701 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12722 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12723 channel->max_tx = tp->txq_max; in tg3_get_channels()
12726 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12727 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12729 if (tp->rxq_req) in tg3_get_channels()
12730 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12732 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12734 if (tp->txq_req) in tg3_get_channels()
12735 channel->tx_count = tp->txq_req; in tg3_get_channels()
12737 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12747 return -EOPNOTSUPP; in tg3_set_channels()
12749 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12750 channel->tx_count > tp->txq_max) in tg3_set_channels()
12751 return -EINVAL; in tg3_set_channels()
12753 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12754 tp->txq_req = channel->tx_count; in tg3_set_channels()
12788 if (!netif_running(tp->dev)) in tg3_set_phys_id()
12789 return -EAGAIN; in tg3_set_phys_id()
12811 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12823 if (tp->hw_stats) in tg3_get_ethtool_stats()
12871 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12872 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12885 cnt = pci_read_vpd(tp->pdev, pos, in tg3_vpd_readblock()
12886 len - pos, ptr); in tg3_vpd_readblock()
12887 if (cnt == -ETIMEDOUT || cnt == -EINTR) in tg3_vpd_readblock()
12925 return -EIO; in tg3_test_nvram()
12952 return -EIO; in tg3_test_nvram()
12959 return -EIO; in tg3_test_nvram()
12963 return -ENOMEM; in tg3_test_nvram()
12965 err = -EIO; in tg3_test_nvram()
12997 err = -EIO; in tg3_test_nvram()
13031 err = -EIO; in tg3_test_nvram()
13044 err = -EIO; in tg3_test_nvram()
13060 return -ENOMEM; in tg3_test_nvram()
13101 if (!netif_running(tp->dev)) in tg3_test_link()
13102 return -ENODEV; in tg3_test_link()
13104 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13110 if (tp->link_up) in tg3_test_link()
13117 return -EIO; in tg3_test_link()
13298 /* Determine the read-only value. */ in tg3_test_registers()
13301 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13308 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13313 * make sure the read-only bits are not changed and the in tg3_test_registers()
13320 /* Test the read-only bits. */ in tg3_test_registers()
13335 netdev_err(tp->dev, in tg3_test_registers()
13338 return -EIO; in tg3_test_registers()
13354 return -EIO; in tg3_do_mem_test()
13464 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13466 tnapi = &tp->napi[0]; in tg3_run_loopback()
13467 rnapi = &tp->napi[0]; in tg3_run_loopback()
13468 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13470 rnapi = &tp->napi[1]; in tg3_run_loopback()
13472 tnapi = &tp->napi[1]; in tg3_run_loopback()
13474 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13476 err = -EIO; in tg3_run_loopback()
13479 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13481 return -ENOMEM; in tg3_run_loopback()
13484 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13499 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13503 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13514 th->check = 0; in tg3_run_loopback()
13545 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); in tg3_run_loopback()
13546 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
13548 return -EIO; in tg3_run_loopback()
13551 val = tnapi->tx_prod; in tg3_run_loopback()
13552 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13553 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13555 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13556 rnapi->coal_now); in tg3_run_loopback()
13560 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13565 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13567 return -EIO; in tg3_run_loopback()
13570 tnapi->tx_prod++; in tg3_run_loopback()
13575 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13576 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13582 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13587 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13588 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13589 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13594 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13597 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13605 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13606 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13607 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13609 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13610 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13613 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13614 - ETH_FCS_LEN; in tg3_run_loopback()
13620 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13627 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13628 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13634 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13635 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13638 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13639 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13644 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, in tg3_run_loopback()
13671 int err = -EIO; in tg3_test_loopback()
13675 if (tp->dma_limit) in tg3_test_loopback()
13676 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13678 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13679 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13681 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13707 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13726 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13770 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13771 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13776 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13779 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13788 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13790 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13792 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13802 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13806 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13809 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13827 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13831 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13836 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13841 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13844 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13849 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13868 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13879 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13881 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13882 return -EFAULT; in tg3_hwtstamp_set()
13885 return -EINVAL; in tg3_hwtstamp_set()
13889 return -ERANGE; in tg3_hwtstamp_set()
13893 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13896 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13900 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13904 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13908 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13912 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13916 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13920 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13924 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13928 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13932 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13936 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13940 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13944 return -ERANGE; in tg3_hwtstamp_set()
13947 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13949 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13956 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13957 -EFAULT : 0; in tg3_hwtstamp_set()
13966 return -EOPNOTSUPP; in tg3_hwtstamp_get()
13972 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
14014 return -ERANGE; in tg3_hwtstamp_get()
14017 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
14018 -EFAULT : 0; in tg3_hwtstamp_get()
14029 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14030 return -EAGAIN; in tg3_ioctl()
14031 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14037 data->phy_id = tp->phy_addr; in tg3_ioctl()
14043 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14047 return -EAGAIN; in tg3_ioctl()
14049 spin_lock_bh(&tp->lock); in tg3_ioctl()
14050 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14051 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14052 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14054 data->val_out = mii_regval; in tg3_ioctl()
14060 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14064 return -EAGAIN; in tg3_ioctl()
14066 spin_lock_bh(&tp->lock); in tg3_ioctl()
14067 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14068 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14069 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14083 return -EOPNOTSUPP; in tg3_ioctl()
14090 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14107 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14108 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14109 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14110 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14111 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14112 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14113 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14114 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14115 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14116 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14117 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14118 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14119 return -EINVAL; in tg3_set_coalesce()
14122 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14123 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14124 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14125 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14126 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14127 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14128 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14129 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14130 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14134 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14144 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14145 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14146 return -EOPNOTSUPP; in tg3_set_eee()
14149 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14150 netdev_warn(tp->dev, in tg3_set_eee()
14152 return -EINVAL; in tg3_set_eee()
14155 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14156 netdev_warn(tp->dev, in tg3_set_eee()
14159 return -EINVAL; in tg3_set_eee()
14162 tp->eee = *edata; in tg3_set_eee()
14164 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14167 if (netif_running(tp->dev)) { in tg3_set_eee()
14181 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14182 netdev_warn(tp->dev, in tg3_get_eee()
14184 return -EOPNOTSUPP; in tg3_get_eee()
14187 *edata = tp->eee; in tg3_get_eee()
14233 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14234 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14235 *stats = tp->net_stats_prev; in tg3_get_stats64()
14236 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14241 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14259 dev->mtu = new_mtu; in tg3_set_mtu()
14345 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14362 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14372 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14391 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14395 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14398 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14401 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14405 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14424 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14425 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14429 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14430 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14433 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14434 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14438 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14439 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14443 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14444 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14448 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14449 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14453 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14454 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14463 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14466 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14469 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14472 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14475 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14478 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14481 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14499 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14503 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14510 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14520 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14545 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14548 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14551 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14554 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14557 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14563 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14566 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14568 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14572 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14576 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14594 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14596 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14605 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14608 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14613 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14616 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14643 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14647 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14657 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14660 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14665 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14672 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14678 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14684 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14690 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14698 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14700 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14712 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14714 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14726 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14734 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14738 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14742 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14749 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14755 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14758 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14761 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14771 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14785 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14787 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14799 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14809 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14812 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14826 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14837 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14840 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14850 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14873 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14874 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14879 tp->nvram_size = in tg3_get_5720_nvram_info()
14903 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14909 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14911 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14925 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14933 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14938 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14942 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14946 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14968 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14977 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14983 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14989 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14993 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
15003 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15046 netdev_warn(tp->dev, in tg3_nvram_init()
15053 tp->nvram_size = 0; in tg3_nvram_init()
15079 if (tp->nvram_size == 0) in tg3_nvram_init()
15168 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15170 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15180 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15181 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15198 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15211 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15244 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15247 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15249 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15261 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15265 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15269 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15276 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15281 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15284 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15289 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15295 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15299 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15301 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15309 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15310 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15313 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15317 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15319 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15320 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15337 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15344 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15348 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15350 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15353 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15359 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15370 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15372 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15383 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15387 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15390 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15423 return -EBUSY; in tg3_ape_otp_read()
15442 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15446 * configuration is a 32-bit value that straddles the alignment boundary.
15447 * We do two 32-bit reads and then shift and merge the results.
15479 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15480 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15485 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15494 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15495 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15496 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15497 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15498 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15499 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15501 tp->old_link = -1; in tg3_phy_init_link_config()
15512 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15515 switch (tp->pci_fn) { in tg3_phy_probe()
15517 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15520 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15523 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15526 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15532 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15533 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15534 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15549 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15563 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15565 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15567 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15569 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15581 tp->phy_id = p->phy_id; in tg3_phy_probe()
15590 return -ENODEV; in tg3_phy_probe()
15593 if (!tp->phy_id || in tg3_phy_probe()
15594 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15595 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15599 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15608 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15610 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15612 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15614 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15615 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15616 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15621 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15622 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15639 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15640 tp->link_config.flowctrl); in tg3_phy_probe()
15648 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15702 if (len >= sizeof(tp->fw_ver)) in tg3_read_vpd()
15703 len = sizeof(tp->fw_ver) - 1; in tg3_read_vpd()
15704 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15705 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, in tg3_read_vpd()
15722 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15726 if (tp->board_part_number[0]) in tg3_read_vpd()
15731 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15732 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15733 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15734 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15735 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15739 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15740 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15741 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15742 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15743 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15744 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15745 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15746 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15750 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15751 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15752 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15753 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15754 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15755 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15756 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15757 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15758 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15759 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15760 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15761 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15765 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15766 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15767 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15768 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15769 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15770 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15771 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15772 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15776 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15779 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15819 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15822 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15826 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15832 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15843 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15861 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15868 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15908 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15909 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15913 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15914 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15915 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15939 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15947 offset += val - start; in tg3_read_mgmtfw_ver()
15949 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15951 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15952 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15961 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15962 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15966 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15997 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
16002 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
16004 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
16032 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16033 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16042 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16046 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16071 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16094 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16097 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16098 if (peer && peer != tp->pdev) in tg3_find_peer()
16102 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16103 * tp->pdev in that case. in tg3_find_peer()
16106 peer = tp->pdev; in tg3_find_peer()
16121 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16130 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16131 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16132 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16133 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16134 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16135 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16136 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16137 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16138 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16139 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16140 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16142 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16143 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16144 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16145 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16146 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16147 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16148 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16149 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16150 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16151 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16156 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16163 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16166 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16214 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16217 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16219 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16244 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16246 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16248 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16253 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16255 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16257 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16258 tp->misc_host_ctrl); in tg3_get_invariants()
16268 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16271 * non-zero address during special cycles. However, only in tg3_get_invariants()
16272 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16299 while (pci_id->vendor != 0) { in tg3_get_invariants()
16300 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16306 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16307 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16310 if (bridge->subordinate && in tg3_get_invariants()
16311 (bridge->subordinate->number == in tg3_get_invariants()
16312 tp->pdev->bus->number)) { in tg3_get_invariants()
16332 while (pci_id->vendor != 0) { in tg3_get_invariants()
16333 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16334 pci_id->device, in tg3_get_invariants()
16340 if (bridge->subordinate && in tg3_get_invariants()
16341 (bridge->subordinate->number <= in tg3_get_invariants()
16342 tp->pdev->bus->number) && in tg3_get_invariants()
16343 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16344 tp->pdev->bus->number)) { in tg3_get_invariants()
16353 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16354 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16355 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16360 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16368 if (bridge && bridge->subordinate && in tg3_get_invariants()
16369 (bridge->subordinate->number <= in tg3_get_invariants()
16370 tp->pdev->bus->number) && in tg3_get_invariants()
16371 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16372 tp->pdev->bus->number)) { in tg3_get_invariants()
16382 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16404 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16406 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16422 tp->fw_needed = NULL; in tg3_get_invariants()
16426 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16429 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16431 tp->irq_max = 1; in tg3_get_invariants()
16439 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16449 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16453 tp->txq_max = 1; in tg3_get_invariants()
16454 tp->rxq_max = 1; in tg3_get_invariants()
16455 if (tp->irq_max > 1) { in tg3_get_invariants()
16456 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16461 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16469 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16486 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16489 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16494 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16516 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16517 if (!tp->pcix_cap) { in tg3_get_invariants()
16518 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16519 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16520 return -EIO; in tg3_get_invariants()
16537 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16538 &tp->pci_cacheline_sz); in tg3_get_invariants()
16539 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16540 &tp->pci_lat_timer); in tg3_get_invariants()
16542 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16543 tp->pci_lat_timer = 64; in tg3_get_invariants()
16544 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16545 tp->pci_lat_timer); in tg3_get_invariants()
16548 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16557 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16571 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16572 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16576 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16577 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16581 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16583 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16592 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16596 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16600 tp->read32 = tg3_read32; in tg3_get_invariants()
16601 tp->write32 = tg3_write32; in tg3_get_invariants()
16602 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16603 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16604 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16605 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16609 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16620 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16624 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16626 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16630 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16631 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16632 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16633 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16634 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16635 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16637 iounmap(tp->regs); in tg3_get_invariants()
16638 tp->regs = NULL; in tg3_get_invariants()
16640 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16642 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16645 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16646 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16647 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16648 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16651 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16665 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16669 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16670 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16672 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16682 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16684 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16689 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16690 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16706 tp->fw_needed = NULL; in tg3_get_invariants()
16716 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16720 tp->ape_hb_interval = in tg3_get_invariants()
16724 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16729 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16732 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16735 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16738 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16743 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16745 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16746 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16748 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16751 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16756 tp->grc_local_ctrl |= in tg3_get_invariants()
16765 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16779 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16786 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16787 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16788 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16792 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16794 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16797 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16805 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16806 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16807 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16808 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16809 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16811 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16816 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16817 if (tp->phy_otp == 0) in tg3_get_invariants()
16818 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16822 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16824 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16826 tp->coalesce_mode = 0; in tg3_get_invariants()
16829 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16836 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16837 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16860 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16870 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16884 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16900 tp->fw_needed = NULL; in tg3_get_invariants()
16914 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16917 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16918 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16919 tp->misc_host_ctrl); in tg3_get_invariants()
16924 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16926 tp->mac_mode = 0; in tg3_get_invariants()
16929 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16933 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16941 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16942 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16945 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16947 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16963 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16965 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16966 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16971 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16979 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16980 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16983 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16985 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16989 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16990 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16991 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16993 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
17001 tp->rx_std_max_post = 8; in tg3_get_invariants()
17004 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17013 struct net_device *dev = tp->dev; in tg3_get_macaddr_sparc()
17014 struct pci_dev *pdev = tp->pdev; in tg3_get_macaddr_sparc()
17015 struct device_node *dp = pci_device_to_OF_node(pdev); in tg3_get_macaddr_sparc() local
17019 addr = of_get_property(dp, "local-mac-address", &len); in tg3_get_macaddr_sparc()
17021 memcpy(dev->dev_addr, addr, ETH_ALEN); in tg3_get_macaddr_sparc()
17024 return -ENODEV; in tg3_get_macaddr_sparc()
17029 struct net_device *dev = tp->dev; in tg3_get_default_macaddr_sparc()
17031 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN); in tg3_get_default_macaddr_sparc()
17038 struct net_device *dev = tp->dev; in tg3_get_device_address()
17049 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); in tg3_get_device_address()
17050 if (!err && is_valid_ether_addr(&dev->dev_addr[0])) in tg3_get_device_address()
17064 if (tp->pci_fn & 1) in tg3_get_device_address()
17066 if (tp->pci_fn > 1) in tg3_get_device_address()
17074 dev->dev_addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17075 dev->dev_addr[1] = (hi >> 0) & 0xff; in tg3_get_device_address()
17078 dev->dev_addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17079 dev->dev_addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17080 dev->dev_addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17081 dev->dev_addr[5] = (lo >> 0) & 0xff; in tg3_get_device_address()
17084 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); in tg3_get_device_address()
17091 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); in tg3_get_device_address()
17092 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); in tg3_get_device_address()
17099 dev->dev_addr[5] = lo & 0xff; in tg3_get_device_address()
17100 dev->dev_addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17101 dev->dev_addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17102 dev->dev_addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17103 dev->dev_addr[1] = hi & 0xff; in tg3_get_device_address()
17104 dev->dev_addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17108 if (!is_valid_ether_addr(&dev->dev_addr[0])) { in tg3_get_device_address()
17113 return -EINVAL; in tg3_get_device_address()
17127 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17160 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17163 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17164 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17294 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17313 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17315 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17317 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17324 ret = -ENODEV; in tg3_do_test_dma()
17356 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17359 ret = -ENOMEM; in tg3_test_dma()
17363 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17366 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17373 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17377 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17379 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17392 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17394 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17399 tp->dma_rwctrl |= in tg3_test_dma()
17405 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17408 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17410 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17414 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17418 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17423 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17433 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17435 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17438 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17448 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17449 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17450 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17461 dev_err(&tp->pdev->dev, in tg3_test_dma()
17470 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17480 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17482 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17483 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17484 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17487 dev_err(&tp->pdev->dev, in tg3_test_dma()
17490 ret = -ENODEV; in tg3_test_dma()
17501 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17508 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17509 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17512 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17515 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17519 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17527 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17529 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17531 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17534 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17536 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17538 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17541 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17543 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17545 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17548 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17550 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17554 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17556 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17558 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17561 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17563 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17565 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17568 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17570 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17572 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17576 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17577 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17582 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17642 strcat(str, ":32-bit"); in tg3_bus_string()
17644 strcat(str, ":64-bit"); in tg3_bus_string()
17650 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17653 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17654 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17655 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17656 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17657 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17658 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17659 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17660 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17661 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17662 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17664 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17666 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17667 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17668 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17669 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17673 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17674 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17675 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17694 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17700 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17708 err = -ENOMEM; in tg3_init_one()
17712 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17715 tp->pdev = pdev; in tg3_init_one()
17716 tp->dev = dev; in tg3_init_one()
17717 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17718 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17719 tp->irq_sync = 1; in tg3_init_one()
17720 tp->pcierr_recovery = false; in tg3_init_one()
17723 tp->msg_enable = tg3_debug; in tg3_init_one()
17725 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17745 tp->misc_host_ctrl = in tg3_init_one()
17751 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17755 * are running in big-endian mode. in tg3_init_one()
17757 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17760 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17762 spin_lock_init(&tp->lock); in tg3_init_one()
17763 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17764 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17766 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17767 if (!tp->regs) { in tg3_init_one()
17768 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17769 err = -ENOMEM; in tg3_init_one()
17773 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17774 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17775 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17776 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17777 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17778 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17779 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17780 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17781 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17782 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17786 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17787 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17789 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17790 if (!tp->aperegs) { in tg3_init_one()
17791 dev_err(&pdev->dev, in tg3_init_one()
17793 err = -ENOMEM; in tg3_init_one()
17798 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17799 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17801 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17802 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17803 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17804 dev->irq = pdev->irq; in tg3_init_one()
17808 dev_err(&pdev->dev, in tg3_init_one()
17814 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17815 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17816 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17837 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17846 dev_err(&pdev->dev, in tg3_init_one()
17885 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17887 dev->vlan_features |= features; in tg3_init_one()
17891 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17899 dev->hw_features |= features; in tg3_init_one()
17900 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17902 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17903 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17904 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17910 tp->rx_pending = 63; in tg3_init_one()
17915 dev_err(&pdev->dev, in tg3_init_one()
17923 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17924 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17926 tnapi->tp = tp; in tg3_init_one()
17927 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17929 tnapi->int_mbox = intmbx; in tg3_init_one()
17935 tnapi->consmbox = rcvmbx; in tg3_init_one()
17936 tnapi->prodmbox = sndmbx; in tg3_init_one()
17939 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17941 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17959 sndmbx -= 0x4; in tg3_init_one()
17979 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17998 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
18004 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
18005 &tp->pdev->dev); in tg3_init_one()
18006 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
18007 tp->ptp_clock = NULL; in tg3_init_one()
18011 tp->board_part_number, in tg3_init_one()
18014 dev->dev_addr); in tg3_init_one()
18016 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
18019 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
18020 ethtype = "10/100Base-TX"; in tg3_init_one()
18021 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
18022 ethtype = "1000Base-SX"; in tg3_init_one()
18024 ethtype = "10/100/1000Base-T"; in tg3_init_one()
18029 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18030 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18034 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
18036 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18039 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
18040 tp->dma_rwctrl, in tg3_init_one()
18041 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
18042 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
18049 if (tp->aperegs) { in tg3_init_one()
18050 iounmap(tp->aperegs); in tg3_init_one()
18051 tp->aperegs = NULL; in tg3_init_one()
18055 if (tp->regs) { in tg3_init_one()
18056 iounmap(tp->regs); in tg3_init_one()
18057 tp->regs = NULL; in tg3_init_one()
18081 release_firmware(tp->fw); in tg3_remove_one()
18091 if (tp->aperegs) { in tg3_remove_one()
18092 iounmap(tp->aperegs); in tg3_remove_one()
18093 tp->aperegs = NULL; in tg3_remove_one()
18095 if (tp->regs) { in tg3_remove_one()
18096 iounmap(tp->regs); in tg3_remove_one()
18097 tp->regs = NULL; in tg3_remove_one()
18183 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18223 * tg3_io_error_detected - called when PCI error is detected
18242 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18247 tp->pcierr_recovery = true; in tg3_io_error_detected()
18282 * tg3_io_slot_reset - called after the pci bus has been reset.
18285 * Restart the card from scratch, as if from a cold-boot.
18300 dev_err(&pdev->dev, in tg3_io_slot_reset()
18301 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18331 * tg3_io_resume - called when traffic can start flowing again.
18369 tp->pcierr_recovery = false; in tg3_io_resume()