Lines Matching +full:0 +full:x209c
19 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
20 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
21 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
22 #define MVPP2_RX_FIFO_INIT_REG 0x64
23 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
24 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
27 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
28 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
30 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
32 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
33 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
36 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
37 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
39 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
40 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
42 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
46 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
50 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
51 #define MVPP2_PRS_PORT_LU_MAX 0xf
52 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
54 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
55 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
57 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
58 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
60 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
61 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
63 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
64 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
65 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
66 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
67 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240
68 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244
69 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0)
72 #define MVPP22_RSS_INDEX 0x1500
76 #define MVPP22_RXQ2RSS_TABLE 0x1504
78 #define MVPP22_RSS_TABLE_ENTRY 0x1508
79 #define MVPP22_RSS_WIDTH 0x150c
82 #define MVPP2_CLS_MODE_REG 0x1800
83 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
84 #define MVPP2_CLS_PORT_WAY_REG 0x1810
86 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
88 #define MVPP2_CLS_LKP_TBL_REG 0x1818
89 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
92 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
93 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
94 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0)
95 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7
98 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff
101 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
102 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7
104 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f
106 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7
108 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
109 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f
112 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
114 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
115 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
116 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
120 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00
121 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10
122 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14
123 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18
124 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c
125 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20
127 #define MVPP22_CLS_C2_HIT_CTR 0x1b50
128 #define MVPP22_CLS_C2_ACT 0x1b60
129 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19)
130 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)
131 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)
132 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)
133 #define MVPP22_CLS_C2_ATTR0 0x1b64
134 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)
135 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f
137 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21)
138 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7
140 #define MVPP22_CLS_C2_ATTR1 0x1b68
141 #define MVPP22_CLS_C2_ATTR2 0x1b6c
143 #define MVPP22_CLS_C2_ATTR3 0x1b70
146 #define MVPP2_RXQ_NUM_REG 0x2040
147 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
149 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
150 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
151 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
152 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
154 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
155 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
157 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
158 #define MVPP2_RXQ_THRESH_REG 0x204c
159 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
160 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
161 #define MVPP2_RXQ_INDEX_REG 0x2050
162 #define MVPP2_TXQ_NUM_REG 0x2080
163 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
164 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
165 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
166 #define MVPP2_TXQ_THRESH_REG 0x2094
168 #define MVPP2_TXQ_THRESH_MASK 0x3fff
169 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
170 #define MVPP2_TXQ_INDEX_REG 0x2098
171 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
172 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
177 #define MVPP2_TXQ_PENDING_REG 0x20a0
178 #define MVPP2_TXQ_PENDING_MASK 0x3fff
179 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
180 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
182 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
183 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
185 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
186 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
187 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
189 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
191 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
193 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
194 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
195 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
198 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
199 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
200 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
201 #define MVPP2_BASE_ADDR_ENABLE 0x4060
204 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
205 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
206 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
207 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
208 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
209 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
210 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
211 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
212 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
213 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
214 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
215 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
218 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
221 #define MVPP22_AXI_CODE_CACHE_OFFS 0
224 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
225 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
226 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
232 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
233 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0
235 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
236 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
237 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
240 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
241 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
244 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
245 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
247 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
248 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
249 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
252 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
253 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
254 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
255 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
257 ((version) == MVPP21 ? 0xffff : 0xff)
258 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
266 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
267 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
268 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
269 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
271 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
274 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
275 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
276 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
277 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
278 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
279 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
280 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
281 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
282 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
283 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
284 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
285 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8
287 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
288 #define MVPP2_BM_START_MASK BIT(0)
292 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
296 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
299 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
300 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
305 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
306 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
307 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
308 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
309 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
310 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
311 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
313 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
314 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
317 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
318 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
319 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
320 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
324 #define MVPP2_CTRS_IDX 0x7040
325 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700
326 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704
329 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
330 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
331 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
333 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
334 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
335 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
336 #define MVPP2_TXP_MTU_MAX 0x7FFFF
337 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
338 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
339 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
341 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
342 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
343 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
344 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
345 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
347 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
348 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
349 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
350 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
353 #define MVPP2_TX_SNOOP_REG 0x8800
354 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
358 #define MVPP2_SRC_ADDR_MIDDLE 0x24
359 #define MVPP2_SRC_ADDR_HIGH 0x28
360 #define MVPP2_PHY_AN_CFG0_REG 0x34
362 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
363 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
366 #define MVPP2_GMAC_CTRL_0_REG 0x0
367 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
370 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
372 #define MVPP2_GMAC_CTRL_1_REG 0x4
378 #define MVPP2_GMAC_CTRL_2_REG 0x8
379 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
385 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
386 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
399 #define MVPP2_GMAC_STATUS0 0x10
400 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
407 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
409 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
412 #define MVPP22_GMAC_INT_STAT 0x20
414 #define MVPP22_GMAC_INT_MASK 0x24
416 #define MVPP22_GMAC_CTRL_4_REG 0x90
417 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
423 #define MVPP22_GMAC_INT_SUM_MASK 0xa4
426 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
429 #define MVPP22_XLG_CTRL0_REG 0x100
430 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
435 #define MVPP22_XLG_CTRL1_REG 0x104
436 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
437 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
438 #define MVPP22_XLG_STATUS 0x10c
439 #define MVPP22_XLG_STATUS_LINK_UP BIT(0)
440 #define MVPP22_XLG_INT_STAT 0x114
442 #define MVPP22_XLG_INT_MASK 0x118
444 #define MVPP22_XLG_CTRL3_REG 0x11c
446 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
448 #define MVPP22_XLG_EXT_INT_MASK 0x15c
451 #define MVPP22_XLG_CTRL4_REG 0x184
458 #define MVPP22_SMI_MISC_CFG_REG 0x1204
461 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
463 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
467 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
470 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
471 #define MVPP22_MPCS_CTRL 0x14
473 #define MVPP22_MPCS_CLK_RESET 0x14c
474 #define MAC_CLK_RESET_SD_TX BIT(0)
481 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
482 #define MVPP22_XPCS_CFG0 0x0
487 #define GENCONF_SOFT_RESET1 0x1108
489 #define GENCONF_PORT_CTRL0 0x1110
493 #define GENCONF_PORT_CTRL1 0x1114
496 #define GENCONF_CTRL0 0x1120
497 #define GENCONF_CTRL0_PORT0_RGMII BIT(0)
525 #define MVPP2_IP_LBDT_TYPE 0xfffa
533 #define MVPP2_TX_MTU_MAX 0x7ffff
575 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
576 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
577 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
578 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200
579 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80
580 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
581 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
584 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa
585 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3
616 #define MVPP2_F_LOOPBACK BIT(0)
620 MVPP2_TAG_TYPE_NONE = 0,
663 #define MVPP21_ADDR_SPACE_SZ 0
670 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000
671 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400
672 #define MVPP22_MIB_COUNTERS_OFFSET 0x0
673 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100
675 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0
676 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8
677 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc
678 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10
679 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18
680 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c
681 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20
682 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24
683 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28
684 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c
685 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30
686 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
687 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38
688 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40
689 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48
690 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c
691 #define MVPP2_MIB_FC_SENT 0x54
692 #define MVPP2_MIB_FC_RCVD 0x58
693 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c
694 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60
695 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64
696 #define MVPP2_MIB_OVERSIZE_RCVD 0x68
697 #define MVPP2_MIB_JABBER_RCVD 0x6c
698 #define MVPP2_MIB_MAC_RCV_ERROR 0x70
699 #define MVPP2_MIB_BAD_CRC_EVENT 0x74
700 #define MVPP2_MIB_COLLISION 0x78
701 #define MVPP2_MIB_LATE_COLLISION 0x7c
866 #define MVPP2_TXD_L3_OFF_SHIFT 0
879 #define MVPP2_RXD_ERR_CRC 0x0
1035 /* RX queue number, in the range 0-31 for physical RXQs */
1064 /* Pool number in the range 0-7 */