Lines Matching +full:8 +full:bit
13 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
18 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
24 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
27 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
28 #define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
34 #define DEV_EEE_CFG_EEE_ENA BIT(22)
38 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
39 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
40 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
44 #define DEV_EEE_CFG_PORT_LPI BIT(0)
60 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
61 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
65 #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
66 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
67 #define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
76 #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
77 #define DEV_MAC_TAGS_CFG_PB_ENA BIT(1)
78 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
82 #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
86 #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
87 #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
88 #define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
89 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
90 #define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
99 #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
100 #define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
101 #define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
105 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
106 #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
112 #define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
113 #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
121 #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
122 #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
123 #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
124 #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
125 #define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
126 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
127 #define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
128 #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
129 #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
130 #define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
134 #define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
135 #define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
136 #define PCS1G_CFG_PCS_ENA BIT(0)
140 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
141 #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
145 #define PCS1G_SD_CFG_SD_SEL BIT(8)
146 #define PCS1G_SD_CFG_SD_POL BIT(4)
147 #define PCS1G_SD_CFG_SD_ENA BIT(0)
154 #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
155 #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
156 #define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
163 #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
167 #define PCS1G_LB_CFG_RA_ENA BIT(4)
168 #define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
169 #define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
173 #define PCS1G_DBG_CFG_UDLT BIT(0)
177 #define PCS1G_CDET_CFG_CDET_ENA BIT(0)
184 #define PCS1G_ANEG_STATUS_PR BIT(4)
185 #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
186 #define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
195 #define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
196 #define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
197 #define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
203 #define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
204 #define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
210 #define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
211 #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
212 #define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
216 #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
222 #define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
223 #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
224 #define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
225 #define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
226 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
227 #define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
228 #define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
234 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
235 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
236 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
237 #define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
238 #define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
242 #define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
243 #define DEV_PCS_FX100_CFG_SD_POL BIT(25)
244 #define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
245 #define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
246 #define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
253 #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
257 #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
258 #define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
259 #define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
260 #define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
264 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
265 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
266 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
267 #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
268 #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
269 #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
270 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
271 #define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
272 #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
273 #define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)