Lines Matching +full:8 +full:bit
11 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
25 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
26 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
27 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
28 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
35 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
36 #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
37 #define HSIO_PLL5G_CFG1_ROT_DIR BIT(16)
38 #define HSIO_PLL5G_CFG1_READBACK_DATA_SEL BIT(15)
39 #define HSIO_PLL5G_CFG1_RC_ENABLE BIT(14)
43 #define HSIO_PLL5G_CFG1_QUARTER_RATE BIT(5)
44 #define HSIO_PLL5G_CFG1_PWD_TX BIT(4)
45 #define HSIO_PLL5G_CFG1_PWD_RX BIT(3)
46 #define HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA BIT(2)
47 #define HSIO_PLL5G_CFG1_HALF_RATE BIT(1)
48 #define HSIO_PLL5G_CFG1_FORCE_SET_ENA BIT(0)
50 #define HSIO_PLL5G_CFG2_ENA_TEST_MODE BIT(30)
51 #define HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP BIT(29)
52 #define HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT BIT(28)
53 #define HSIO_PLL5G_CFG2_ENA_FBTESTOUT BIT(27)
54 #define HSIO_PLL5G_CFG2_ENA_RCPLL BIT(26)
55 #define HSIO_PLL5G_CFG2_ENA_CP2 BIT(25)
56 #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1 BIT(24)
60 #define HSIO_PLL5G_CFG2_ENA_CLK_BYPASS BIT(15)
61 #define HSIO_PLL5G_CFG2_PWD_AMPCTRL_N BIT(14)
62 #define HSIO_PLL5G_CFG2_ENA_AMPCTRL BIT(13)
63 #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
64 #define HSIO_PLL5G_CFG2_FRC_FSM_POR BIT(11)
65 #define HSIO_PLL5G_CFG2_DISABLE_FSM_POR BIT(10)
69 #define HSIO_PLL5G_CFG2_EN_RESET_OVERRUN BIT(4)
70 #define HSIO_PLL5G_CFG2_EN_RESET_LIM_DET BIT(3)
71 #define HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET BIT(2)
72 #define HSIO_PLL5G_CFG2_DISABLE_FSM BIT(1)
73 #define HSIO_PLL5G_CFG2_ENA_GAIN_TEST BIT(0)
81 #define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
82 #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
83 #define HSIO_PLL5G_CFG3_SEL_FBDCLK BIT(16)
84 #define HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD BIT(15)
85 #define HSIO_PLL5G_CFG3_RST_FB_N BIT(14)
86 #define HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH BIT(13)
87 #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
88 #define HSIO_PLL5G_CFG3_FORCE_HI BIT(11)
89 #define HSIO_PLL5G_CFG3_FORCE_ENA BIT(10)
90 #define HSIO_PLL5G_CFG3_FORCE_CP BIT(9)
91 #define HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA BIT(8)
107 #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
111 #define HSIO_PLL5G_CFG6_REFCLK_SRC BIT(19)
115 #define HSIO_PLL5G_CFG6_DIV125REF_SEL(x) (((x) << 8) & GENMASK(15, 8))
116 #define HSIO_PLL5G_CFG6_DIV125REF_SEL_M GENMASK(15, 8)
117 #define HSIO_PLL5G_CFG6_DIV125REF_SEL_X(x) (((x) & GENMASK(15, 8)) >> 8)
118 #define HSIO_PLL5G_CFG6_ENA_REFCLKC2 BIT(7)
119 #define HSIO_PLL5G_CFG6_ENA_FBCLKC2 BIT(6)
123 #define HSIO_PLL5G_STATUS0_RANGE_LIM BIT(12)
124 #define HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR BIT(11)
125 #define HSIO_PLL5G_STATUS0_CALIBRATION_ERR BIT(10)
126 #define HSIO_PLL5G_STATUS0_CALIBRATION_DONE BIT(9)
127 #define HSIO_PLL5G_STATUS0_READBACK_DATA(x) (((x) << 1) & GENMASK(8, 1))
128 #define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
129 #define HSIO_PLL5G_STATUS0_READBACK_DATA_X(x) (((x) & GENMASK(8, 1)) >> 1)
130 #define HSIO_PLL5G_STATUS0_LOCK_STATUS BIT(0)
144 #define HSIO_PLL5G_STATUS1_FSM_LOCK BIT(0)
146 #define HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST BIT(31)
147 #define HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE BIT(30)
160 #define HSIO_PLL5G_BIST_STAT0_PLLB_BUSY BIT(2)
161 #define HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N BIT(1)
162 #define HSIO_PLL5G_BIST_STAT0_PLLB_FAIL BIT(0)
170 #define HSIO_RCOMP_CFG0_PWD_ENA BIT(13)
171 #define HSIO_RCOMP_CFG0_RUN_CAL BIT(12)
175 #define HSIO_RCOMP_CFG0_MODE_SEL(x) (((x) << 8) & GENMASK(9, 8))
176 #define HSIO_RCOMP_CFG0_MODE_SEL_M GENMASK(9, 8)
177 #define HSIO_RCOMP_CFG0_MODE_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
178 #define HSIO_RCOMP_CFG0_FORCE_ENA BIT(4)
182 #define HSIO_RCOMP_STATUS_BUSY BIT(12)
183 #define HSIO_RCOMP_STATUS_DELTA_ALERT BIT(7)
195 #define HSIO_SYNC_ETH_CFG_RECO_CLK_ENA BIT(0)
197 #define HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA BIT(0)
205 #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL(x) (((x) << 8) & GENMASK(10, 8))
206 #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M GENMASK(10, 8)
207 #define HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X(x) (((x) & GENMASK(10, 8)) >> 8)
211 #define HSIO_S1G_DES_CFG_DES_SWAP_ANA BIT(4)
215 #define HSIO_S1G_DES_CFG_DES_SWAP_HYST BIT(0)
217 #define HSIO_S1G_IB_CFG_IB_FX100_ENA BIT(27)
224 #define HSIO_S1G_IB_CFG_IB_HYST_LEV BIT(14)
225 #define HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM BIT(13)
226 #define HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING BIT(12)
227 #define HSIO_S1G_IB_CFG_IB_ENA_DETLEV BIT(11)
228 #define HSIO_S1G_IB_CFG_IB_ENA_HYST BIT(10)
229 #define HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP BIT(9)
230 #define HSIO_S1G_IB_CFG_IB_EQ_GAIN(x) (((x) << 6) & GENMASK(8, 6))
231 #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_M GENMASK(8, 6)
232 #define HSIO_S1G_IB_CFG_IB_EQ_GAIN_X(x) (((x) & GENMASK(8, 6)) >> 6)
248 #define HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL BIT(9)
249 #define HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG BIT(8)
256 #define HSIO_S1G_SER_CFG_SER_IDLE BIT(9)
257 #define HSIO_S1G_SER_CFG_SER_DEEMPH BIT(8)
258 #define HSIO_S1G_SER_CFG_SER_CPMD_SEL BIT(7)
259 #define HSIO_S1G_SER_CFG_SER_SWAP_CPMD BIT(6)
263 #define HSIO_S1G_SER_CFG_SER_ENHYS BIT(3)
264 #define HSIO_S1G_SER_CFG_SER_BIG_WIN BIT(2)
265 #define HSIO_S1G_SER_CFG_SER_EN_WIN BIT(1)
266 #define HSIO_S1G_SER_CFG_SER_ENALI BIT(0)
268 #define HSIO_S1G_COMMON_CFG_SYS_RST BIT(31)
269 #define HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(21)
270 #define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
271 #define HSIO_S1G_COMMON_CFG_PWD_RX BIT(17)
272 #define HSIO_S1G_COMMON_CFG_PWD_TX BIT(16)
276 #define HSIO_S1G_COMMON_CFG_ENA_DIRECT BIT(12)
277 #define HSIO_S1G_COMMON_CFG_ENA_ELOOP BIT(11)
278 #define HSIO_S1G_COMMON_CFG_ENA_FLOOP BIT(10)
279 #define HSIO_S1G_COMMON_CFG_ENA_ILOOP BIT(9)
280 #define HSIO_S1G_COMMON_CFG_ENA_PLOOP BIT(8)
281 #define HSIO_S1G_COMMON_CFG_HRATE BIT(7)
282 #define HSIO_S1G_COMMON_CFG_IF_MODE BIT(0)
284 #define HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2 BIT(22)
285 #define HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2 BIT(21)
286 #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(x) (((x) << 8) & GENMASK(15, 8))
287 #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M GENMASK(15, 8)
288 #define HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X(x) (((x) & GENMASK(15, 8)) >> 8)
289 #define HSIO_S1G_PLL_CFG_PLL_FSM_ENA BIT(7)
290 #define HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(6)
291 #define HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(5)
292 #define HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL BIT(3)
294 #define HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(12)
295 #define HSIO_S1G_PLL_STATUS_PLL_CAL_ERR BIT(11)
296 #define HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(10)
300 #define HSIO_S1G_DFT_CFG0_LAZYBIT BIT(31)
301 #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
308 #define HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
309 #define HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
310 #define HSIO_S1G_DFT_CFG0_RX_DFT_ENA BIT(2)
311 #define HSIO_S1G_DFT_CFG0_TX_DFT_ENA BIT(0)
313 #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
314 #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
315 #define HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
319 #define HSIO_S1G_DFT_CFG1_TX_JI_ENA BIT(3)
320 #define HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
321 #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
322 #define HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
324 #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
325 #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
326 #define HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
330 #define HSIO_S1G_DFT_CFG2_RX_JI_ENA BIT(3)
331 #define HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
332 #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
333 #define HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
335 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
339 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
340 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
341 #define HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
348 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
349 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
350 #define HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
351 #define HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
352 #define HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
353 #define HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
354 #define HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
355 #define HSIO_S1G_MISC_CFG_LANE_RST BIT(0)
357 #define HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
358 #define HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
359 #define HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
360 #define HSIO_S1G_DFT_STATUS_BIST_ACTIVE BIT(3)
361 #define HSIO_S1G_DFT_STATUS_BIST_NOSYNC BIT(2)
362 #define HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
363 #define HSIO_S1G_DFT_STATUS_BIST_ERROR BIT(0)
365 #define HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
367 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT BIT(31)
368 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT BIT(30)
369 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(x) ((x) & GENMASK(8, 0))
370 #define HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M GENMASK(8, 0)
375 #define HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA BIT(7)
376 #define HSIO_S6G_DIG_CFG_SIGDET_TESTMODE BIT(6)
383 #define HSIO_S6G_DFT_CFG0_LAZYBIT BIT(31)
384 #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
391 #define HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS BIT(4)
392 #define HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA BIT(3)
393 #define HSIO_S6G_DFT_CFG0_RX_DFT_ENA BIT(2)
394 #define HSIO_S6G_DFT_CFG0_TX_DFT_ENA BIT(0)
396 #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
397 #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M GENMASK(17, 8)
398 #define HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
402 #define HSIO_S6G_DFT_CFG1_TX_JI_ENA BIT(3)
403 #define HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL BIT(2)
404 #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR BIT(1)
405 #define HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA BIT(0)
407 #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL(x) (((x) << 8) & GENMASK(17, 8))
408 #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M GENMASK(17, 8)
409 #define HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X(x) (((x) & GENMASK(17, 8)) >> 8)
413 #define HSIO_S6G_DFT_CFG2_RX_JI_ENA BIT(3)
414 #define HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL BIT(2)
415 #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR BIT(1)
416 #define HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA BIT(0)
418 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA BIT(20)
422 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH(x) (((x) << 8) & GENMASK(15, 8))
423 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M GENMASK(15, 8)
424 #define HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X(x) (((x) & GENMASK(15, 8)) >> 8)
434 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP BIT(10)
435 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE BIT(9)
436 #define HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA BIT(8)
437 #define HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA BIT(7)
438 #define HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA BIT(6)
439 #define HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA BIT(5)
440 #define HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA BIT(4)
441 #define HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA BIT(3)
442 #define HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA BIT(2)
443 #define HSIO_S6G_MISC_CFG_LANE_RST BIT(0)
454 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
455 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M GENMASK(8, 6)
456 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
460 #define HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT BIT(8)
461 #define HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE BIT(7)
462 #define HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED BIT(6)
463 #define HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR BIT(5)
464 #define HSIO_S6G_DFT_STATUS_BIST_ACTIVE BIT(3)
465 #define HSIO_S6G_DFT_STATUS_BIST_NOSYNC BIT(2)
466 #define HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N BIT(1)
467 #define HSIO_S6G_DFT_STATUS_BIST_ERROR BIT(0)
469 #define HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL BIT(0)
477 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL(x) (((x) << 8) & GENMASK(9, 8))
478 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_M GENMASK(9, 8)
479 #define HSIO_S6G_DES_CFG_DES_CPMD_SEL_X(x) (((x) & GENMASK(9, 8)) >> 8)
483 #define HSIO_S6G_DES_CFG_DES_SWAP_HYST BIT(4)
487 #define HSIO_S6G_DES_CFG_DES_SWAP_ANA BIT(0)
492 #define HSIO_S6G_IB_CFG_IB_VBULK_SEL BIT(28)
514 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(x) (((x) << 7) & GENMASK(8, 7))
515 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M GENMASK(8, 7)
516 #define HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X(x) (((x) & GENMASK(8, 7)) >> 7)
517 #define HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA BIT(6)
518 #define HSIO_S6G_IB_CFG_IB_SIG_DET_ENA BIT(5)
519 #define HSIO_S6G_IB_CFG_IB_CONCUR BIT(4)
520 #define HSIO_S6G_IB_CFG_IB_CAL_ENA BIT(3)
521 #define HSIO_S6G_IB_CFG_IB_SAM_ENA BIT(2)
522 #define HSIO_S6G_IB_CFG_IB_EQZ_ENA BIT(1)
523 #define HSIO_S6G_IB_CFG_IB_REG_ENA BIT(0)
531 #define HSIO_S6G_IB_CFG1_IB_SCALY(x) (((x) << 8) & GENMASK(11, 8))
532 #define HSIO_S6G_IB_CFG1_IB_SCALY_M GENMASK(11, 8)
533 #define HSIO_S6G_IB_CFG1_IB_SCALY_X(x) (((x) & GENMASK(11, 8)) >> 8)
534 #define HSIO_S6G_IB_CFG1_IB_FILT_HP BIT(7)
535 #define HSIO_S6G_IB_CFG1_IB_FILT_MID BIT(6)
536 #define HSIO_S6G_IB_CFG1_IB_FILT_LP BIT(5)
537 #define HSIO_S6G_IB_CFG1_IB_FILT_OFFSET BIT(4)
538 #define HSIO_S6G_IB_CFG1_IB_FRC_HP BIT(3)
539 #define HSIO_S6G_IB_CFG1_IB_FRC_MID BIT(2)
540 #define HSIO_S6G_IB_CFG1_IB_FRC_LP BIT(1)
541 #define HSIO_S6G_IB_CFG1_IB_FRC_OFFSET BIT(0)
603 #define HSIO_S6G_OB_CFG_OB_IDLE BIT(31)
604 #define HSIO_S6G_OB_CFG_OB_ENA1V_MODE BIT(30)
605 #define HSIO_S6G_OB_CFG_OB_POL BIT(29)
612 #define HSIO_S6G_OB_CFG_OB_R_ADJ_MUX BIT(17)
613 #define HSIO_S6G_OB_CFG_OB_R_ADJ_PDR BIT(16)
617 #define HSIO_S6G_OB_CFG_OB_R_COR BIT(10)
618 #define HSIO_S6G_OB_CFG_OB_SEL_RCTRL BIT(9)
619 #define HSIO_S6G_OB_CFG_OB_SR_H BIT(8)
626 #define HSIO_S6G_OB_CFG1_OB_ENA_CAS(x) (((x) << 6) & GENMASK(8, 6))
627 #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_M GENMASK(8, 6)
628 #define HSIO_S6G_OB_CFG1_OB_ENA_CAS_X(x) (((x) & GENMASK(8, 6)) >> 6)
632 #define HSIO_S6G_SER_CFG_SER_4TAP_ENA BIT(8)
633 #define HSIO_S6G_SER_CFG_SER_CPMD_SEL BIT(7)
634 #define HSIO_S6G_SER_CFG_SER_SWAP_CPMD BIT(6)
638 #define HSIO_S6G_SER_CFG_SER_ENHYS BIT(3)
639 #define HSIO_S6G_SER_CFG_SER_BIG_WIN BIT(2)
640 #define HSIO_S6G_SER_CFG_SER_EN_WIN BIT(1)
641 #define HSIO_S6G_SER_CFG_SER_ENALI BIT(0)
643 #define HSIO_S6G_COMMON_CFG_SYS_RST BIT(17)
644 #define HSIO_S6G_COMMON_CFG_SE_DIV2_ENA BIT(16)
645 #define HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA BIT(15)
646 #define HSIO_S6G_COMMON_CFG_ENA_LANE BIT(14)
647 #define HSIO_S6G_COMMON_CFG_PWD_RX BIT(13)
648 #define HSIO_S6G_COMMON_CFG_PWD_TX BIT(12)
652 #define HSIO_S6G_COMMON_CFG_ENA_DIRECT BIT(8)
653 #define HSIO_S6G_COMMON_CFG_ENA_ELOOP BIT(7)
654 #define HSIO_S6G_COMMON_CFG_ENA_FLOOP BIT(6)
655 #define HSIO_S6G_COMMON_CFG_ENA_ILOOP BIT(5)
656 #define HSIO_S6G_COMMON_CFG_ENA_PLOOP BIT(4)
657 #define HSIO_S6G_COMMON_CFG_HRATE BIT(3)
658 #define HSIO_S6G_COMMON_CFG_QRATE BIT(2)
665 #define HSIO_S6G_PLL_CFG_PLL_DIV4 BIT(15)
666 #define HSIO_S6G_PLL_CFG_PLL_ENA_ROT BIT(14)
670 #define HSIO_S6G_PLL_CFG_PLL_FSM_ENA BIT(5)
671 #define HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA BIT(4)
672 #define HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA BIT(3)
673 #define HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL BIT(2)
674 #define HSIO_S6G_PLL_CFG_PLL_ROT_DIR BIT(1)
675 #define HSIO_S6G_PLL_CFG_PLL_ROT_FRQ BIT(0)
677 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N BIT(5)
678 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P BIT(4)
679 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK BIT(3)
680 #define HSIO_S6G_ACJTAG_CFG_OB_DIRECT BIT(2)
681 #define HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA BIT(1)
682 #define HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA BIT(0)
690 #define HSIO_S6G_IB_STATUS0_IB_CAL_DONE BIT(8)
691 #define HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT BIT(7)
692 #define HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT BIT(6)
693 #define HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT BIT(5)
694 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT BIT(4)
695 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD BIT(3)
696 #define HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR BIT(2)
697 #define HSIO_S6G_IB_STATUS0_IB_OFFSDIR BIT(1)
698 #define HSIO_S6G_IB_STATUS0_IB_SIG_DET BIT(0)
712 #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N BIT(2)
713 #define HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P BIT(1)
714 #define HSIO_S6G_ACJTAG_STATUS_IB_DIRECT BIT(0)
716 #define HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE BIT(10)
717 #define HSIO_S6G_PLL_STATUS_PLL_CAL_ERR BIT(9)
718 #define HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR BIT(8)
740 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT BIT(31)
741 #define HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT BIT(30)
745 #define HSIO_HW_CFG_DEV2G5_10_MODE BIT(6)
746 #define HSIO_HW_CFG_DEV1G_9_MODE BIT(5)
747 #define HSIO_HW_CFG_DEV1G_6_MODE BIT(4)
748 #define HSIO_HW_CFG_DEV1G_5_MODE BIT(3)
749 #define HSIO_HW_CFG_DEV1G_4_MODE BIT(2)
750 #define HSIO_HW_CFG_PCIE_ENA BIT(1)
751 #define HSIO_HW_CFG_QSGMII_ENA BIT(0)
753 #define HSIO_HW_QSGMII_CFG_SHYST_DIS BIT(3)
754 #define HSIO_HW_QSGMII_CFG_E_DET_ENA BIT(2)
755 #define HSIO_HW_QSGMII_CFG_USE_I1_ENA BIT(1)
756 #define HSIO_HW_QSGMII_CFG_FLIP_LANES BIT(0)
761 #define HSIO_HW_QSGMII_STAT_SYNC BIT(0)
763 #define HSIO_CLK_CFG_CLKDIV_PHY(x) (((x) << 1) & GENMASK(8, 1))
764 #define HSIO_CLK_CFG_CLKDIV_PHY_M GENMASK(8, 1)
765 #define HSIO_CLK_CFG_CLKDIV_PHY_X(x) (((x) & GENMASK(8, 1)) >> 1)
766 #define HSIO_CLK_CFG_CLKDIV_PHY_DIS BIT(0)
768 #define HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD BIT(5)
769 #define HSIO_TEMP_SENSOR_CTRL_FORCE_RUN BIT(4)
770 #define HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST BIT(3)
771 #define HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP BIT(2)
772 #define HSIO_TEMP_SENSOR_CTRL_FORCE_CLK BIT(1)
773 #define HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA BIT(0)
775 #define HSIO_TEMP_SENSOR_CFG_RUN_WID(x) (((x) << 8) & GENMASK(15, 8))
776 #define HSIO_TEMP_SENSOR_CFG_RUN_WID_M GENMASK(15, 8)
777 #define HSIO_TEMP_SENSOR_CFG_RUN_WID_X(x) (((x) & GENMASK(15, 8)) >> 8)
781 #define HSIO_TEMP_SENSOR_STAT_TEMP_VALID BIT(8)