Lines Matching full:phydev
65 static void r_rc_cal_reset(struct phy_device *phydev) in r_rc_cal_reset() argument
68 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010); in r_rc_cal_reset()
71 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000); in r_rc_cal_reset()
74 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_b0_afe_config_init() argument
79 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048); in bcm7xxx_28nm_b0_afe_config_init()
82 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b); in bcm7xxx_28nm_b0_afe_config_init()
87 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20); in bcm7xxx_28nm_b0_afe_config_init()
90 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b); in bcm7xxx_28nm_b0_afe_config_init()
93 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm7xxx_28nm_b0_afe_config_init()
95 r_rc_cal_reset(phydev); in bcm7xxx_28nm_b0_afe_config_init()
98 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); in bcm7xxx_28nm_b0_afe_config_init()
101 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); in bcm7xxx_28nm_b0_afe_config_init()
104 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_b0_afe_config_init()
107 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); in bcm7xxx_28nm_b0_afe_config_init()
110 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); in bcm7xxx_28nm_b0_afe_config_init()
115 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_d0_afe_config_init() argument
118 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
121 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
124 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
127 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
130 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
133 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
136 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
141 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
144 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
147 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
150 r_rc_cal_reset(phydev); in bcm7xxx_28nm_d0_afe_config_init()
155 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_e0_plus_afe_config_init() argument
158 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
161 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
164 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
169 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
172 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
175 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
178 r_rc_cal_reset(phydev); in bcm7xxx_28nm_e0_plus_afe_config_init()
183 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_a0_patch_afe_config_init() argument
186 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
189 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
192 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
195 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
198 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
201 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
203 r_rc_cal_reset(phydev); in bcm7xxx_28nm_a0_patch_afe_config_init()
208 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) in bcm7xxx_28nm_config_init() argument
210 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); in bcm7xxx_28nm_config_init()
211 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); in bcm7xxx_28nm_config_init()
219 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_config_init()
222 phydev_name(phydev), phydev->drv->name, rev, patch); in bcm7xxx_28nm_config_init()
229 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_config_init()
234 ret = bcm7xxx_28nm_b0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
237 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
243 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
246 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev); in bcm7xxx_28nm_config_init()
255 ret = bcm_phy_downshift_get(phydev, &count); in bcm7xxx_28nm_config_init()
260 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_config_init()
264 return bcm_phy_enable_apd(phydev, true); in bcm7xxx_28nm_config_init()
267 static int bcm7xxx_28nm_resume(struct phy_device *phydev) in bcm7xxx_28nm_resume() argument
272 ret = bcm7xxx_28nm_config_init(phydev); in bcm7xxx_28nm_resume()
281 return genphy_config_aneg(phydev); in bcm7xxx_28nm_resume()
303 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_01_afe_config_init() argument
308 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_01_afe_config_init()
314 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
319 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
323 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
329 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
333 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_01_afe_config_init()
340 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
349 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_apd_enable() argument
354 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, in bcm7xxx_28nm_ephy_apd_enable()
360 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in bcm7xxx_28nm_ephy_apd_enable()
366 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
374 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev) in bcm7xxx_28nm_ephy_eee_enable() argument
379 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_28nm_ephy_eee_enable()
385 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
389 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
395 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
399 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
404 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
408 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
414 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
418 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
425 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
431 phy_write(phydev, MII_BMCR, in bcm7xxx_28nm_ephy_eee_enable()
437 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) in bcm7xxx_28nm_ephy_config_init() argument
439 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm7xxx_28nm_ephy_config_init()
443 phydev_name(phydev), phydev->drv->name, rev); in bcm7xxx_28nm_ephy_config_init()
450 phy_read(phydev, MII_BMSR); in bcm7xxx_28nm_ephy_config_init()
454 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev); in bcm7xxx_28nm_ephy_config_init()
459 ret = bcm7xxx_28nm_ephy_eee_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
463 return bcm7xxx_28nm_ephy_apd_enable(phydev); in bcm7xxx_28nm_ephy_config_init()
466 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev) in bcm7xxx_28nm_ephy_resume() argument
471 ret = bcm7xxx_28nm_ephy_config_init(phydev); in bcm7xxx_28nm_ephy_resume()
475 return genphy_config_aneg(phydev); in bcm7xxx_28nm_ephy_resume()
478 static int bcm7xxx_config_init(struct phy_device *phydev) in bcm7xxx_config_init() argument
483 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO); in bcm7xxx_config_init()
484 phy_read(phydev, MII_BCM7XXX_AUX_MODE); in bcm7xxx_config_init()
487 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, in bcm7xxx_config_init()
493 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
497 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
499 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
502 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
512 static int bcm7xxx_suspend(struct phy_device *phydev) in bcm7xxx_suspend() argument
529 ret = phy_write(phydev, in bcm7xxx_suspend()
539 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev, in bcm7xxx_28nm_get_tunable() argument
545 return bcm_phy_downshift_get(phydev, (u8 *)data); in bcm7xxx_28nm_get_tunable()
551 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev, in bcm7xxx_28nm_set_tunable() argument
560 ret = bcm_phy_downshift_set(phydev, count); in bcm7xxx_28nm_set_tunable()
573 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE); in bcm7xxx_28nm_set_tunable()
577 return genphy_restart_aneg(phydev); in bcm7xxx_28nm_set_tunable()
580 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev, in bcm7xxx_28nm_get_phy_stats() argument
583 struct bcm7xxx_phy_priv *priv = phydev->priv; in bcm7xxx_28nm_get_phy_stats()
585 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm7xxx_28nm_get_phy_stats()
588 static int bcm7xxx_28nm_probe(struct phy_device *phydev) in bcm7xxx_28nm_probe() argument
592 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm7xxx_28nm_probe()
596 phydev->priv = priv; in bcm7xxx_28nm_probe()
598 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm7xxx_28nm_probe()
599 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm7xxx_28nm_probe()