23 #include <dt-bindings/net/ti-dp83867.h>
126 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in dp83867_config_intr()
149 		(struct dp83867_private *)phydev->priv;  in dp83867_config_port_mirroring()
154 	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)  in dp83867_config_port_mirroring()
167 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
168 	struct device *dev = &phydev->mdio.dev;  in dp83867_of_init()
169 	struct device_node *of_node = dev->of_node;  in dp83867_of_init()
173 		return -ENODEV;  in dp83867_of_init()
175 	dp83867->io_impedance = -EINVAL;  in dp83867_of_init()
178 	ret = of_property_read_u32(of_node, "ti,clk-output-sel",  in dp83867_of_init()
179 				   &dp83867->clk_output_sel);  in dp83867_of_init()
180 	if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)  in dp83867_of_init()
181 		/* Keep the default value if ti,clk-output-sel is not set  in dp83867_of_init()
184 		dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;  in dp83867_of_init()
186 	if (of_property_read_bool(of_node, "ti,max-output-impedance"))  in dp83867_of_init()
187 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;  in dp83867_of_init()
188 	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))  in dp83867_of_init()
189 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;  in dp83867_of_init()
191 	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,  in dp83867_of_init()
192 					"ti,dp83867-rxctrl-strap-quirk");  in dp83867_of_init()
194 	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",  in dp83867_of_init()
195 				   &dp83867->rx_id_delay);  in dp83867_of_init()
197 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
198 	     phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))  in dp83867_of_init()
201 	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",  in dp83867_of_init()
202 				   &dp83867->tx_id_delay);  in dp83867_of_init()
204 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
205 	     phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))  in dp83867_of_init()
208 	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))  in dp83867_of_init()
209 		dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;  in dp83867_of_init()
211 	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))  in dp83867_of_init()
212 		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;  in dp83867_of_init()
214 	return of_property_read_u32(of_node, "ti,fifo-depth",  in dp83867_of_init()
215 				   &dp83867->fifo_depth);  in dp83867_of_init()
230 	if (!phydev->priv) {  in dp83867_config_init()
231 		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),  in dp83867_config_init()
234 			return -ENOMEM;  in dp83867_config_init()
236 		phydev->priv = dp83867;  in dp83867_config_init()
241 		dp83867 = (struct dp83867_private *)phydev->priv;  in dp83867_config_init()
245 	if (dp83867->rxctrl_strap_quirk) {  in dp83867_config_init()
256 		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);  in dp83867_config_init()
279 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in dp83867_config_init()
282 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in dp83867_config_init()
285 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in dp83867_config_init()
290 		delay = (dp83867->rx_id_delay |  in dp83867_config_init()
291 			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));  in dp83867_config_init()
296 		if (dp83867->io_impedance >= 0) {  in dp83867_config_init()
301 			val |= dp83867->io_impedance &  in dp83867_config_init()
309 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {  in dp83867_config_init()
339 	/* Enable Interrupt output INT_OE in CFG3 register */  in dp83867_config_init()
346 	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)  in dp83867_config_init()
349 	/* Clock output selection if muxing property is set */  in dp83867_config_init()
350 	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {  in dp83867_config_init()
353 		val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);  in dp83867_config_init()