2  * Marvell 10G 88x3310 PHY driver
4  * Based upon the ID registers, this PHY appears to be a mixture of IPs
7  * There appears to be several different data paths through the PHY which
8  * are automatically managed by the PHY.  The following has been determined
9  * via observation and experimentation for a setup using single-lane Serdes:
11  *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12  *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13  *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
17  *        XAUI PHYXS -- <appropriate PCS as above>
27 #include <linux/phy.h>
42 	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
46 	MV_AN_CTRL1000		= 0x8000, /* 1000base-T control register */
47 	MV_AN_STAT1000		= 0x8001, /* 1000base-T status register */
109 		*value = ((temp & 0xff) - 75) * 1000;  in mv3310_hwmon_read()
114 	return -EOPNOTSUPP;  in mv3310_hwmon_read()
179 	struct device *dev = &phydev->mdio.dev;  in mv3310_hwmon_probe()
180 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);  in mv3310_hwmon_probe()
183 	priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);  in mv3310_hwmon_probe()
184 	if (!priv->hwmon_name)  in mv3310_hwmon_probe()
185 		return -ENODEV;  in mv3310_hwmon_probe()
187 	for (i = j = 0; priv->hwmon_name[i]; i++) {  in mv3310_hwmon_probe()
188 		if (isalnum(priv->hwmon_name[i])) {  in mv3310_hwmon_probe()
190 				priv->hwmon_name[j] = priv->hwmon_name[i];  in mv3310_hwmon_probe()
194 	priv->hwmon_name[j] = '\0';  in mv3310_hwmon_probe()
204 	priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,  in mv3310_hwmon_probe()
205 				priv->hwmon_name, phydev,  in mv3310_hwmon_probe()
208 	return PTR_ERR_OR_ZERO(priv->hwmon_dev);  in mv3310_hwmon_probe()
228 	if (!phydev->is_c45 ||  in mv3310_probe()
229 	    (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)  in mv3310_probe()
230 		return -ENODEV;  in mv3310_probe()
237 		dev_warn(&phydev->mdio.dev,  in mv3310_probe()
238 			 "PHY failed to boot firmware, status=%04x\n", ret);  in mv3310_probe()
239 		return -ENODEV;  in mv3310_probe()
242 	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);  in mv3310_probe()
244 		return -ENOMEM;  in mv3310_probe()
246 	dev_set_drvdata(&phydev->mdio.dev, priv);  in mv3310_probe()
271 	/* Check that the PHY interface type is compatible */  in mv3310_config_init()
272 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&  in mv3310_config_init()
273 	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&  in mv3310_config_init()
274 	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&  in mv3310_config_init()
275 	    phydev->interface != PHY_INTERFACE_MODE_10GKR)  in mv3310_config_init()
276 		return -ENODEV;  in mv3310_config_init()
281 	if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {  in mv3310_config_init()
353 		dev_warn(&phydev->mdio.dev,  in mv3310_config_init()
354 			 "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",  in mv3310_config_init()
357 	phydev->supported &= mask;  in mv3310_config_init()
358 	phydev->advertising &= phydev->supported;  in mv3310_config_init()
370 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;  in mv3310_config_aneg()
372 	if (phydev->autoneg == AUTONEG_DISABLE) {  in mv3310_config_aneg()
380 	phydev->advertising &= phydev->supported;  in mv3310_config_aneg()
381 	advertising = phydev->advertising;  in mv3310_config_aneg()
432 	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||  in mv3310_update_interface()
433 	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {  in mv3310_update_interface()
434 		/* The PHY automatically switches its serdes interface (and  in mv3310_update_interface()
435 		 * active PHYXS instance) between Cisco SGMII and 10GBase-KR  in mv3310_update_interface()
437 		 * phydev->interface to communicate this to the MAC. Only do  in mv3310_update_interface()
438 		 * this if we are already in either SGMII or 10GBase-KR mode.  in mv3310_update_interface()
440 		if (phydev->speed == SPEED_10000)  in mv3310_update_interface()
441 			phydev->interface = PHY_INTERFACE_MODE_10GKR;  in mv3310_update_interface()
442 		else if (phydev->speed >= SPEED_10 &&  in mv3310_update_interface()
443 			 phydev->speed < SPEED_10000)  in mv3310_update_interface()
444 			phydev->interface = PHY_INTERFACE_MODE_SGMII;  in mv3310_update_interface()
448 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
451 	phydev->link = 1;  in mv3310_read_10gbr_status()
452 	phydev->speed = SPEED_10000;  in mv3310_read_10gbr_status()
453 	phydev->duplex = DUPLEX_FULL;  in mv3310_read_10gbr_status()
462 	u32 mmd_mask = phydev->c45_ids.devices_in_package;  in mv3310_read_status()
472 	phydev->speed = SPEED_UNKNOWN;  in mv3310_read_status()
473 	phydev->duplex = DUPLEX_UNKNOWN;  in mv3310_read_status()
474 	phydev->lp_advertising = 0;  in mv3310_read_status()
475 	phydev->link = 0;  in mv3310_read_status()
476 	phydev->pause = 0;  in mv3310_read_status()
477 	phydev->asym_pause = 0;  in mv3310_read_status()
478 	phydev->mdix = 0;  in mv3310_read_status()
491 	phydev->link = val > 0 ? 1 : 0;  in mv3310_read_status()
507 		phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);  in mv3310_read_status()
509 		if (phydev->autoneg == AUTONEG_ENABLE)  in mv3310_read_status()
513 	if (phydev->autoneg != AUTONEG_ENABLE) {  in mv3310_read_status()
519 	if (phydev->speed == SPEED_10000) {  in mv3310_read_status()
530 			phydev->mdix = ETH_TP_MDI_X;  in mv3310_read_status()
533 			phydev->mdix = ETH_TP_MDI;  in mv3310_read_status()
536 			phydev->mdix = ETH_TP_MDI_INVALID;  in mv3310_read_status()
579 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");