Lines Matching full:phydev
126 static int vsc85xx_phy_page_set(struct phy_device *phydev, u16 page) in vsc85xx_phy_page_set() argument
130 rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_page_set()
134 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
141 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
142 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
151 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
152 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
157 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
161 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
170 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
175 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
185 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
189 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED); in vsc85xx_mdix_set()
193 reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL); in vsc85xx_mdix_set()
199 rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val); in vsc85xx_mdix_set()
203 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_mdix_set()
207 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
210 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
215 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED); in vsc85xx_downshift_get()
219 reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc85xx_downshift_get()
225 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_downshift_get()
231 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
240 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
247 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED); in vsc85xx_downshift_set()
251 reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc85xx_downshift_set()
254 rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val); in vsc85xx_downshift_set()
258 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_downshift_set()
264 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
272 u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
274 mutex_lock(&phydev->lock); in vsc85xx_wol_set()
275 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
284 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
285 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
286 phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
288 phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
289 phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
290 phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
297 phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
298 phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
299 phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
301 phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
302 phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
303 phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
306 reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
311 phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
313 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_wol_set()
319 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
321 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
326 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
328 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
333 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
336 mutex_unlock(&phydev->lock); in vsc85xx_wol_set()
341 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
350 mutex_lock(&phydev->lock); in vsc85xx_wol_get()
351 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
355 reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
359 pwd[0] = phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
360 pwd[1] = phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
361 pwd[2] = phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
369 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_wol_get()
372 mutex_unlock(&phydev->lock); in vsc85xx_wol_get()
376 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
380 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
404 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
408 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
419 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
427 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
432 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
440 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
445 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
446 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_edge_rate_cntl_set()
449 reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_edge_rate_cntl_set()
452 rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_edge_rate_cntl_set()
455 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_edge_rate_cntl_set()
458 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
463 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
469 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
470 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
487 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
491 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
494 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
499 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
504 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
505 mutex_lock(&phydev->lock); in vsc85xx_default_config()
506 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_default_config()
510 reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL); in vsc85xx_default_config()
513 phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val); in vsc85xx_default_config()
514 rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); in vsc85xx_default_config()
517 mutex_unlock(&phydev->lock); in vsc85xx_default_config()
522 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
527 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
533 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
539 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
545 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
548 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
550 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
554 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
558 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
562 rc = vsc85xx_led_cntl_set(phydev, 1, vsc8531->led_1_mode); in vsc85xx_config_init()
566 rc = vsc85xx_led_cntl_set(phydev, 0, vsc8531->led_0_mode); in vsc85xx_config_init()
570 rc = genphy_config_init(phydev); in vsc85xx_config_init()
575 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
579 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
580 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
585 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
589 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
590 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
593 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
596 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
602 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
606 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
610 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
613 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
617 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
621 return genphy_read_status(phydev); in vsc85xx_read_status()
624 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
630 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
634 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
638 phydev->priv = vsc8531; in vsc85xx_probe()
643 led_mode = vsc85xx_dt_led_mode_get(phydev, "vsc8531,led-0-mode", in vsc85xx_probe()
649 led_mode = vsc85xx_dt_led_mode_get(phydev, "vsc8531,led-1-mode", in vsc85xx_probe()