22 #define MII_VSC82X4_EXT_PAGE_16E	0x10
23 #define MII_VSC82X4_EXT_PAGE_17E	0x11
24 #define MII_VSC82X4_EXT_PAGE_18E	0x12
27 #define MII_VSC8244_EXT_CON1           0x17
28 #define MII_VSC8244_EXTCON1_INIT       0x0000
29 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK	0x0c00
30 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK	0x0300
31 #define MII_VSC8244_EXTCON1_TX_SKEW	0x0800
32 #define MII_VSC8244_EXTCON1_RX_SKEW	0x0200
35 #define MII_VSC8244_IMASK		0x19
36 #define MII_VSC8244_IMASK_IEN		0x8000
37 #define MII_VSC8244_IMASK_SPEED		0x4000
38 #define MII_VSC8244_IMASK_LINK		0x2000
39 #define MII_VSC8244_IMASK_DUPLEX	0x1000
40 #define MII_VSC8244_IMASK_MASK		0xf000
42 #define MII_VSC8221_IMASK_MASK		0xa000
45 #define MII_VSC8244_ISTAT		0x1a
46 #define MII_VSC8244_ISTAT_STATUS	0x8000
47 #define MII_VSC8244_ISTAT_SPEED		0x4000
48 #define MII_VSC8244_ISTAT_LINK		0x2000
49 #define MII_VSC8244_ISTAT_DUPLEX	0x1000
52 #define MII_VSC8244_AUX_CONSTAT		0x1c
53 #define MII_VSC8244_AUXCONSTAT_INIT	0x0000
54 #define MII_VSC8244_AUXCONSTAT_DUPLEX	0x0020
55 #define MII_VSC8244_AUXCONSTAT_SPEED	0x0018
56 #define MII_VSC8244_AUXCONSTAT_GBIT	0x0010
57 #define MII_VSC8244_AUXCONSTAT_100	0x0008
59 #define MII_VSC8221_AUXCONSTAT_INIT	0x0004 /* need to set this bit? */
60 #define MII_VSC8221_AUXCONSTAT_RESERVED	0x0004
63 #define MII_VSC82X4_EXT_PAGE_ACCESS	0x1f
66 #define MII_VSC8601_EPHY_CTL		0x17
69 #define PHY_ID_VSC8234			0x000fc620
70 #define PHY_ID_VSC8244			0x000fc6c0
71 #define PHY_ID_VSC8514			0x00070670
72 #define PHY_ID_VSC8572			0x000704d0
73 #define PHY_ID_VSC8574			0x000704a0
74 #define PHY_ID_VSC8601			0x00070420
75 #define PHY_ID_VSC7385			0x00070450
76 #define PHY_ID_VSC7388			0x00070480
77 #define PHY_ID_VSC7395			0x00070550
78 #define PHY_ID_VSC7398			0x00070580
79 #define PHY_ID_VSC8662			0x00070660
80 #define PHY_ID_VSC8221			0x000fc550
81 #define PHY_ID_VSC8211			0x000fc4b0
94 	if (extcon < 0)  in vsc824x_add_skew()
114 	if (err < 0)  in vsc824x_config_init()
123 #define VSC73XX_EXT_PAGE_ACCESS 0x1f
138 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
139 	phy_modify(phydev, 0x0c, 0x0300, 0x0200);  in vsc73xx_config_init()
140 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
142 	/* Config LEDs 0x61 */  in vsc73xx_config_init()
143 	phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061);  in vsc73xx_config_init()
154 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
155 	phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc738x_config_init()
156 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
157 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
158 	phy_modify(phydev, 0x12, 0xff07, 0x0003);  in vsc738x_config_init()
159 	phy_modify(phydev, 0x11, 0x00ff, 0x00a2);  in vsc738x_config_init()
160 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
161 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
162 	phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc738x_config_init()
163 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
167 	rev &= 0x0f;  in vsc738x_config_init()
169 	/* Special quirk for revision 0 */  in vsc738x_config_init()
170 	if (rev == 0) {  in vsc738x_config_init()
171 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
172 		phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc738x_config_init()
173 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
174 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
175 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
176 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
177 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
178 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
179 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
180 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
181 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
182 		phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc738x_config_init()
183 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
184 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
187 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
188 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
190 	if (rev == 0) {  in vsc738x_config_init()
191 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
192 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
193 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
194 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
196 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
197 		phy_modify(phydev, 0x16, 0x0fc0, 0x0240);  in vsc738x_config_init()
198 		phy_modify(phydev, 0x14, 0x6000, 0x4000);  in vsc738x_config_init()
199 		/* bits 14-15 in extended register 0x14 controls DACG amplitude  in vsc738x_config_init()
202 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
203 		phy_modify(phydev, 0x14, 0xe000, 0x6000);  in vsc738x_config_init()
204 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
219 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
220 	phy_modify(phydev, 0x08, 0x0200, 0x0200);  in vsc739x_config_init()
221 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
222 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
223 	phy_modify(phydev, 0x12, 0xff07, 0x0003);  in vsc739x_config_init()
224 	phy_modify(phydev, 0x11, 0x00ff, 0x00a2);  in vsc739x_config_init()
225 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
226 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
227 	phy_modify(phydev, 0x08, 0x0200, 0x0000);  in vsc739x_config_init()
228 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
230 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
231 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
232 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
233 	phy_modify(phydev, 0x16, 0x0fc0, 0x0240);  in vsc739x_config_init()
234 	phy_modify(phydev, 0x14, 0x6000, 0x4000);  in vsc739x_config_init()
235 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
236 	phy_modify(phydev, 0x14, 0xe000, 0x6000);  in vsc739x_config_init()
237 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
251 	return 0;  in vsc73xx_config_aneg()
262 	if (ret < 0)  in vsc8601_add_skew()
271 	int ret = 0;  in vsc8601_config_init()
276 	if (ret < 0)  in vsc8601_config_init()
284 	int err = 0;  in vsc824x_ack_interrupt()
293 	return (err < 0) ? err : 0;  in vsc824x_ack_interrupt()
316 		if (err < 0)  in vsc82xx_config_intr()
319 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
349 		return 0;  in vsc82x4_config_autocross_enable()
351 	/* map extended registers set 0x10 - 0x1e */  in vsc82x4_config_autocross_enable()
352 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
353 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
354 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
355 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
356 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
357 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
358 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
359 	/* map standard registers set 0x10 - 0x1e */  in vsc82x4_config_autocross_enable()
360 	if (ret >= 0)  in vsc82x4_config_autocross_enable()
361 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
363 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
386 		if (ret < 0) /* error */  in vsc82x4_config_aneg()
400 	.phy_id_mask    = 0x000ffff0,
410 	.phy_id_mask	= 0x000fffc0,
420 	.phy_id_mask	= 0x000ffff0,
430 	.phy_id_mask    = 0x000ffff0,
440 	.phy_id_mask    = 0x000ffff0,
450 	.phy_id_mask    = 0x000ffff0,
459 	.phy_id_mask    = 0x000ffff0,
468 	.phy_id_mask    = 0x000ffff0,
477 	.phy_id_mask    = 0x000ffff0,
486 	.phy_id_mask    = 0x000ffff0,
495 	.phy_id_mask    = 0x000ffff0,
505 	.phy_id_mask	= 0x000ffff0,
515 	.phy_id_mask	= 0x000ffff0,
527 	{ PHY_ID_VSC8234, 0x000ffff0 },
528 	{ PHY_ID_VSC8244, 0x000fffc0 },
529 	{ PHY_ID_VSC8514, 0x000ffff0 },
530 	{ PHY_ID_VSC8572, 0x000ffff0 },
531 	{ PHY_ID_VSC8574, 0x000ffff0 },
532 	{ PHY_ID_VSC7385, 0x000ffff0 },
533 	{ PHY_ID_VSC7388, 0x000ffff0 },
534 	{ PHY_ID_VSC7395, 0x000ffff0 },
535 	{ PHY_ID_VSC7398, 0x000ffff0 },
536 	{ PHY_ID_VSC8662, 0x000ffff0 },
537 	{ PHY_ID_VSC8221, 0x000ffff0 },
538 	{ PHY_ID_VSC8211, 0x000ffff0 },