Lines Matching +full:0 +full:xcd00
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_TEREDO_WAKE_BASE 0xc0c4
55 #define PLA_MAR 0xcd00
56 #define PLA_BACKUP 0xd000
57 #define PAL_BDC_CR 0xd1a0
58 #define PLA_TEREDO_TIMER 0xd2cc
59 #define PLA_REALWOW_TIMER 0xd2e8
60 #define PLA_EFUSE_DATA 0xdd00
61 #define PLA_EFUSE_CMD 0xdd02
62 #define PLA_LEDSEL 0xdd90
63 #define PLA_LED_FEATURE 0xdd92
64 #define PLA_PHYAR 0xde00
65 #define PLA_BOOT_CTRL 0xe004
66 #define PLA_GPHY_INTR_IMR 0xe022
67 #define PLA_EEE_CR 0xe040
68 #define PLA_EEEP_CR 0xe080
69 #define PLA_MAC_PWR_CTRL 0xe0c0
70 #define PLA_MAC_PWR_CTRL2 0xe0ca
71 #define PLA_MAC_PWR_CTRL3 0xe0cc
72 #define PLA_MAC_PWR_CTRL4 0xe0ce
73 #define PLA_WDT6_CTRL 0xe428
74 #define PLA_TCR0 0xe610
75 #define PLA_TCR1 0xe612
76 #define PLA_MTPS 0xe615
77 #define PLA_TXFIFO_CTRL 0xe618
78 #define PLA_RSTTALLY 0xe800
79 #define PLA_CR 0xe813
80 #define PLA_CRWECR 0xe81c
81 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
82 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
83 #define PLA_CONFIG5 0xe822
84 #define PLA_PHY_PWR 0xe84c
85 #define PLA_OOB_CTRL 0xe84f
86 #define PLA_CPCR 0xe854
87 #define PLA_MISC_0 0xe858
88 #define PLA_MISC_1 0xe85a
89 #define PLA_OCP_GPHY_BASE 0xe86c
90 #define PLA_TALLYCNT 0xe890
91 #define PLA_SFF_STS_7 0xe8de
92 #define PLA_PHYSTATUS 0xe908
93 #define PLA_BP_BA 0xfc26
94 #define PLA_BP_0 0xfc28
95 #define PLA_BP_1 0xfc2a
96 #define PLA_BP_2 0xfc2c
97 #define PLA_BP_3 0xfc2e
98 #define PLA_BP_4 0xfc30
99 #define PLA_BP_5 0xfc32
100 #define PLA_BP_6 0xfc34
101 #define PLA_BP_7 0xfc36
102 #define PLA_BP_EN 0xfc38
104 #define USB_USB2PHY 0xb41e
105 #define USB_SSPHYLINK2 0xb428
106 #define USB_U2P3_CTRL 0xb460
107 #define USB_CSR_DUMMY1 0xb464
108 #define USB_CSR_DUMMY2 0xb466
109 #define USB_DEV_STAT 0xb808
110 #define USB_CONNECT_TIMER 0xcbf8
111 #define USB_MSC_TIMER 0xcbfc
112 #define USB_BURST_SIZE 0xcfc0
113 #define USB_LPM_CONFIG 0xcfd8
114 #define USB_USB_CTRL 0xd406
115 #define USB_PHY_CTRL 0xd408
116 #define USB_TX_AGG 0xd40a
117 #define USB_RX_BUF_TH 0xd40c
118 #define USB_USB_TIMER 0xd428
119 #define USB_RX_EARLY_TIMEOUT 0xd42c
120 #define USB_RX_EARLY_SIZE 0xd42e
121 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
122 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
123 #define USB_TX_DMA 0xd434
124 #define USB_UPT_RXDMA_OWN 0xd437
125 #define USB_TOLERANCE 0xd490
126 #define USB_LPM_CTRL 0xd41a
127 #define USB_BMU_RESET 0xd4b0
128 #define USB_U1U2_TIMER 0xd4da
129 #define USB_UPS_CTRL 0xd800
130 #define USB_POWER_CUT 0xd80a
131 #define USB_MISC_0 0xd81a
132 #define USB_AFE_CTRL2 0xd824
133 #define USB_UPS_CFG 0xd842
134 #define USB_UPS_FLAGS 0xd848
135 #define USB_WDT11_CTRL 0xe43c
136 #define USB_BP_BA 0xfc26
137 #define USB_BP_0 0xfc28
138 #define USB_BP_1 0xfc2a
139 #define USB_BP_2 0xfc2c
140 #define USB_BP_3 0xfc2e
141 #define USB_BP_4 0xfc30
142 #define USB_BP_5 0xfc32
143 #define USB_BP_6 0xfc34
144 #define USB_BP_7 0xfc36
145 #define USB_BP_EN 0xfc38
146 #define USB_BP_8 0xfc38
147 #define USB_BP_9 0xfc3a
148 #define USB_BP_10 0xfc3c
149 #define USB_BP_11 0xfc3e
150 #define USB_BP_12 0xfc40
151 #define USB_BP_13 0xfc42
152 #define USB_BP_14 0xfc44
153 #define USB_BP_15 0xfc46
154 #define USB_BP2_EN 0xfc48
157 #define OCP_ALDPS_CONFIG 0x2010
158 #define OCP_EEE_CONFIG1 0x2080
159 #define OCP_EEE_CONFIG2 0x2092
160 #define OCP_EEE_CONFIG3 0x2094
161 #define OCP_BASE_MII 0xa400
162 #define OCP_EEE_AR 0xa41a
163 #define OCP_EEE_DATA 0xa41c
164 #define OCP_PHY_STATUS 0xa420
165 #define OCP_NCTL_CFG 0xa42c
166 #define OCP_POWER_CFG 0xa430
167 #define OCP_EEE_CFG 0xa432
168 #define OCP_SRAM_ADDR 0xa436
169 #define OCP_SRAM_DATA 0xa438
170 #define OCP_DOWN_SPEED 0xa442
171 #define OCP_EEE_ABLE 0xa5c4
172 #define OCP_EEE_ADV 0xa5d0
173 #define OCP_EEE_LPABLE 0xa5d2
174 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
175 #define OCP_PHY_PATCH_STAT 0xb800
176 #define OCP_PHY_PATCH_CMD 0xb820
177 #define OCP_ADC_IOFFSET 0xbcfc
178 #define OCP_ADC_CFG 0xbc06
179 #define OCP_SYSCLK_CFG 0xc416
182 #define SRAM_GREEN_CFG 0x8011
183 #define SRAM_LPF_CFG 0x8012
184 #define SRAM_10M_AMP1 0x8080
185 #define SRAM_10M_AMP2 0x8082
186 #define SRAM_IMPEDANCE 0x8084
189 #define RCR_AAP 0x00000001
190 #define RCR_APM 0x00000002
191 #define RCR_AM 0x00000004
192 #define RCR_AB 0x00000008
196 #define RXFIFO_THR1_NORMAL 0x00080002
197 #define RXFIFO_THR1_OOB 0x01800003
200 #define RXFIFO_THR2_FULL 0x00000060
201 #define RXFIFO_THR2_HIGH 0x00000038
202 #define RXFIFO_THR2_OOB 0x0000004a
203 #define RXFIFO_THR2_NORMAL 0x00a0
206 #define RXFIFO_THR3_FULL 0x00000078
207 #define RXFIFO_THR3_HIGH 0x00000048
208 #define RXFIFO_THR3_OOB 0x0000005a
209 #define RXFIFO_THR3_NORMAL 0x0110
212 #define TXFIFO_THR_NORMAL 0x00400008
213 #define TXFIFO_THR_NORMAL2 0x01000008
216 #define ECM_ALDPS 0x0002
219 #define FMC_FCR_MCU_EN 0x0001
222 #define EEEP_CR_EEEP_TX 0x0002
225 #define WDT6_SET_MODE 0x0010
228 #define TCR0_TX_EMPTY 0x0800
229 #define TCR0_AUTO_FIFO 0x0080
232 #define VERSION_MASK 0x7cf0
239 #define TALLY_RESET 0x0001
242 #define CR_RST 0x10
243 #define CR_RE 0x08
244 #define CR_TE 0x04
247 #define CRWECR_NORAML 0x00
248 #define CRWECR_CONFIG 0xc0
251 #define NOW_IS_OOB 0x80
252 #define TXFIFO_EMPTY 0x20
253 #define RXFIFO_EMPTY 0x10
254 #define LINK_LIST_READY 0x02
255 #define DIS_MCU_CLROOB 0x01
259 #define RXDY_GATED_EN 0x0008
262 #define RE_INIT_LL 0x8000
263 #define MCU_BORW_EN 0x4000
266 #define CPCR_RX_VLAN 0x0040
269 #define MAGIC_EN 0x0001
272 #define TEREDO_SEL 0x8000
273 #define TEREDO_WAKE_MASK 0x7f00
274 #define TEREDO_RS_EVENT_MASK 0x00fe
275 #define OOB_TEREDO_EN 0x0001
278 #define ALDPS_PROXY_MODE 0x0001
285 #define LINK_ON_WAKE_EN 0x0010
286 #define LINK_OFF_WAKE_EN 0x0008
289 #define BWF_EN 0x0040
290 #define MWF_EN 0x0020
291 #define UWF_EN 0x0010
292 #define LAN_WAKE_EN 0x0002
295 #define LED_MODE_MASK 0x0700
298 #define TX_10M_IDLE_EN 0x0080
299 #define PFM_PWM_SWITCH 0x0040
302 #define D3_CLK_GATED_EN 0x00004000
303 #define MCU_CLK_RATIO 0x07010f07
304 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
305 #define ALDPS_SPDWN_RATIO 0x0f87
308 #define EEE_SPDWN_RATIO 0x8007
312 #define PKT_AVAIL_SPDWN_EN 0x0100
313 #define SUSPEND_SPDWN_EN 0x0004
314 #define U1U2_SPDWN_EN 0x0002
315 #define L1_SPDWN_EN 0x0001
318 #define PWRSAVE_SPDWN_EN 0x1000
319 #define RXDV_SPDWN_EN 0x0800
320 #define TX10MIDLE_EN 0x0100
321 #define TP100_SPDWN_EN 0x0020
322 #define TP500_SPDWN_EN 0x0010
323 #define TP1000_SPDWN_EN 0x0008
324 #define EEE_SPDWN_EN 0x0001
327 #define GPHY_STS_MSK 0x0001
328 #define SPEED_DOWN_MSK 0x0002
329 #define SPDWN_RXDV_MSK 0x0004
330 #define SPDWN_LINKCHG_MSK 0x0008
333 #define PHYAR_FLAG 0x80000000
336 #define EEE_RX_EN 0x0001
337 #define EEE_TX_EN 0x0002
340 #define AUTOLOAD_DONE 0x0002
343 #define USB2PHY_SUSPEND 0x0001
344 #define USB2PHY_L1 0x0002
347 #define pwd_dn_scale_mask 0x3ffe
351 #define DYNAMIC_BURST 0x0001
354 #define EP4_FULL_FC 0x0001
357 #define STAT_SPEED_MASK 0x0006
358 #define STAT_SPEED_HIGH 0x0000
359 #define STAT_SPEED_FULL 0x0002
362 #define LPM_U1U2_EN BIT(0)
365 #define TX_AGG_MAX_THRESHOLD 0x03
368 #define RX_THR_SUPPER 0x0c350180
369 #define RX_THR_HIGH 0x7a120180
370 #define RX_THR_SLOW 0xffff0180
371 #define RX_THR_B 0x00010001
374 #define TEST_MODE_DISABLE 0x00000001
375 #define TX_SIZE_ADJUST1 0x00000100
378 #define BMU_RESET_EP_IN 0x01
379 #define BMU_RESET_EP_OUT 0x02
382 #define OWN_UPDATE BIT(0)
386 #define POWER_CUT 0x0100
389 #define RESUME_INDICATE 0x0001
392 #define RX_AGG_DISABLE 0x0010
393 #define RX_ZERO_EN 0x0080
396 #define U2P3_ENABLE 0x0001
399 #define PWR_EN 0x0001
400 #define PHASE2_EN 0x0008
405 #define PCUT_STATUS 0x0001
413 #define TIMER11_EN 0x0001
417 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
419 #define LPM_TIMER_MASK 0x0c
420 #define LPM_TIMER_500MS 0x04 /* 500 ms */
421 #define LPM_TIMER_500US 0x0c /* 500 us */
422 #define ROK_EXIT_LPM 0x02
425 #define SEN_VAL_MASK 0xf800
426 #define SEN_VAL_NORMAL 0xa000
427 #define SEL_RXIDLE 0x0100
430 #define SAW_CNT_1MS_MASK 0x0fff
433 #define UPS_FLAGS_R_TUNE BIT(0)
438 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
461 #define ENPWRSAVE 0x8000
462 #define ENPDNPS 0x0200
463 #define LINKENA 0x0100
464 #define DIS_SDSAVE 0x0010
467 #define PHY_STAT_MASK 0x0007
476 #define EEE_CLKDIV_EN 0x8000
477 #define EN_ALDPS 0x0004
478 #define EN_10M_PLLOFF 0x0001
481 #define RG_TXLPI_MSK_HFDUP 0x8000
482 #define RG_MATCLR_EN 0x4000
483 #define EEE_10_CAP 0x2000
484 #define EEE_NWAY_EN 0x1000
485 #define TX_QUIET_EN 0x0200
486 #define RX_QUIET_EN 0x0100
487 #define sd_rise_time_mask 0x0070
489 #define RG_RXLPI_MSK_HFDUP 0x0008
490 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
493 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
494 #define RG_DACQUIET_EN 0x0400
495 #define RG_LDVQUIET_EN 0x0200
496 #define RG_CKRSEL 0x0020
497 #define RG_EEEPRG_EN 0x0010
500 #define fast_snr_mask 0xff80
501 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
502 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
503 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
507 #define FUN_ADDR 0x0000
508 #define FUN_DATA 0x4000
509 /* bit[4:0] device addr */
512 #define CTAP_SHORT_EN 0x0040
513 #define EEE10_EN 0x0010
520 #define EN_10M_BGOFF 0x0080
523 #define TXDIS_STATE 0x01
524 #define ABD_STATE 0x02
533 #define CKADSEL_L 0x0100
534 #define ADC_EN 0x0080
535 #define EN_EMI_L 0x0040
545 #define LPF_AUTO_TUNE 0x8000
548 #define GDAC_IB_UPALL 0x0008
551 #define AMP_DN 0x0200
554 #define RX_DRIVING_MASK 0x6000
557 #define AD_MASK 0xfee0
558 #define EFUSE 0xcfdb
559 #define PASS_THRU_MASK 0x1
562 _1000bps = 0x10,
563 _100bps = 0x08,
564 _10bps = 0x04,
565 LINK_STATUS = 0x02,
566 FULL_DUP = 0x01,
575 #define INTR_LINK 0x0004
577 #define RTL8152_REQT_READ 0xc0
578 #define RTL8152_REQT_WRITE 0x40
579 #define RTL8152_REQ_GET_REGS 0x05
580 #define RTL8152_REQ_SET_REGS 0x05
582 #define BYTE_EN_DWORD 0xff
583 #define BYTE_EN_WORD 0x33
584 #define BYTE_EN_BYTE 0x11
585 #define BYTE_EN_SIX_BYTES 0x3f
586 #define BYTE_EN_START_MASK 0x0f
587 #define BYTE_EN_END_MASK 0xf0
601 RTL8152_UNPLUG = 0,
613 #define VENDOR_ID_REALTEK 0x0bda
614 #define VENDOR_ID_MICROSOFT 0x045e
615 #define VENDOR_ID_SAMSUNG 0x04e8
616 #define VENDOR_ID_LENOVO 0x17ef
617 #define VENDOR_ID_LINKSYS 0x13b1
618 #define VENDOR_ID_NVIDIA 0x0955
619 #define VENDOR_ID_TPLINK 0x2357
621 #define MCU_TYPE_PLA 0x0100
622 #define MCU_TYPE_USB 0x0000
642 #define RX_LEN_MASK 0x7fff
668 #define GTTCPHO_MAX 0x7fU
669 #define TX_LEN_MAX 0x3ffffU
677 #define MSS_MAX 0x7ffU
679 #define TCPHO_MAX 0x7ffU
750 RTL_VER_UNKNOWN = 0,
764 TX_CSUM_SUCCESS = 0,
788 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), in get_registers()
791 if (ret < 0) in get_registers()
792 memset(data, 0xff, size); in get_registers()
811 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), in set_registers()
824 int ret = 0; in generic_ocp_read()
833 if ((u32)index + (u32)size > 0xffff) in generic_ocp_read()
839 if (ret < 0) in generic_ocp_read()
847 if (ret < 0) in generic_ocp_read()
852 size = 0; in generic_ocp_read()
877 if ((u32)index + (u32)size > 0xffff) in generic_ocp_write()
885 if (ret < 0) in generic_ocp_write()
900 if (ret < 0) in generic_ocp_write()
910 if (ret < 0) in generic_ocp_write()
915 size = 0; in generic_ocp_write()
922 if (ret < 0) in generic_ocp_write()
981 data &= 0xffff; in ocp_read_word()
988 u32 mask = 0xffff; in ocp_write_word()
1019 data &= 0xff; in ocp_read_byte()
1026 u32 mask = 0xff; in ocp_write_byte()
1049 ocp_base = addr & 0xf000; in ocp_reg_read()
1055 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_read()
1063 ocp_base = addr & 0xf000; in ocp_reg_write()
1069 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_write()
1138 if (ret < 0) in rtl8152_set_mac_address()
1171 if ((ocp_data & AD_MASK) != 0x1000) in vendor_mac_passthru_addr_read()
1184 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { in vendor_mac_passthru_addr_read()
1190 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || in vendor_mac_passthru_addr_read()
1191 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { in vendor_mac_passthru_addr_read()
1197 if (!(ret == 0 && is_valid_ether_addr(buf))) { in vendor_mac_passthru_addr_read()
1228 if (ret < 0) in set_ethernet_addr()
1232 if (ret < 0) { in set_ethernet_addr()
1284 case 0: in read_bulk_callback()
1377 case 0: /* success */ in intr_callback()
1400 if (INTR_LINK & __le16_to_cpu(d[0])) { in intr_callback()
1403 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1409 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1438 for (i = 0; i < RTL8152_MAX_RX; i++) { in free_all_mem()
1447 for (i = 0; i < RTL8152_MAX_TX; i++) { in free_all_mem()
1482 for (i = 0; i < RTL8152_MAX_RX; i++) { in alloc_all_mem()
1495 urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
1508 for (i = 0; i < RTL8152_MAX_TX; i++) { in alloc_all_mem()
1521 urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
1536 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
1549 return 0; in alloc_all_mem()
1606 if (skb_checksum_help(skb) < 0) in r8152_csum_workaround()
1630 ret = skb_cow_head(skb, 0); in msdn_giant_send_check()
1637 th->check = 0; in msdn_giant_send_check()
1638 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); in msdn_giant_send_check()
1659 swab16(opts2 & 0xffff)); in rtl_rx_vlan_tag()
1666 u32 opts1, opts2 = 0; in r8152_tx_csum()
1676 "Invalid transport offset 0x%x for TSO\n", in r8152_tx_csum()
1707 "Invalid transport offset 0x%x\n", in r8152_tx_csum()
1758 agg->skb_num = 0; in r8152_tx_agg_fill()
1759 agg->skb_len = 0; in r8152_tx_agg_fill()
1794 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { in r8152_tx_agg_fill()
1830 if (ret < 0) in r8152_tx_agg_fill()
1838 if (ret < 0) in r8152_tx_agg_fill()
1878 int ret = 0, work_done = 0; in rx_bottom()
1910 int len_used = 0; in rx_bottom()
1977 urb->actual_length = 0; in rx_bottom()
2026 } while (res == 0); in tx_bottom()
2077 return 0; in r8152_submit_rx()
2091 urb->actual_length = 0; in r8152_submit_rx()
2140 schedule_delayed_work(&tp->schedule, 0); in rtl8152_set_rx_mode()
2160 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2161 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2166 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2167 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2171 mc_filter[1] = 0; in _rtl8152_set_rx_mode()
2172 mc_filter[0] = 0; in _rtl8152_set_rx_mode()
2181 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); in _rtl8152_set_rx_mode()
2182 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); in _rtl8152_set_rx_mode()
2217 schedule_delayed_work(&tp->schedule, 0); in rtl8152_start_xmit()
2246 for (i = 0; i < 1000; i++) { in rtl8152_nic_reset()
2297 int i, ret = 0; in rtl_start_rx()
2300 for (i = 0; i < RTL8152_MAX_RX; i++) { in rtl_start_rx()
2317 urb->actual_length = 0; in rtl_start_rx()
2333 for (i = 0; i < RTL8152_MAX_RX; i++) in rtl_stop_rx()
2339 return 0; in rtl_stop_rx()
2354 return 0; in rtl_enable()
2457 for (i = 0; i < RTL8152_MAX_TX; i++) in rtl_disable()
2462 for (i = 0; i < 1000; i++) { in rtl_disable()
2469 for (i = 0; i < 1000; i++) { in rtl_disable()
2516 if (ret < 0) in rtl8152_set_features()
2541 u32 wolopts = 0; in __rtl_get_wol()
2614 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); in r8153_mac_clk_spd()
2615 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); in r8153_mac_clk_spd()
2616 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); in r8153_mac_clk_spd()
2617 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); in r8153_mac_clk_spd()
2626 memset(u1u2, 0xff, sizeof(u1u2)); in r8153_u1u2en()
2628 memset(u1u2, 0x00, sizeof(u1u2)); in r8153_u1u2en()
2673 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ in r8153b_green_en()
2674 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ in r8153b_green_en()
2675 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
2677 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ in r8153b_green_en()
2678 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ in r8153b_green_en()
2679 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
2686 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); in r8153b_green_en()
2694 for (i = 0; i < 500; i++) { in r8153_phy_status()
2721 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); in r8153b_ups_en()
2722 ocp_data |= BIT(0); in r8153b_ups_en()
2723 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); in r8153b_ups_en()
2730 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); in r8153b_ups_en()
2731 ocp_data &= ~BIT(0); in r8153b_ups_en()
2732 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); in r8153b_ups_en()
2738 data = r8153_phy_status(tp, 0); in r8153b_ups_en()
2799 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); in r8153b_queue_wake()
2801 ocp_data |= BIT(0); in r8153b_queue_wake()
2803 ocp_data &= ~BIT(0); in r8153b_queue_wake()
2804 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); in r8153b_queue_wake()
2806 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); in r8153b_queue_wake()
2807 ocp_data &= ~BIT(0); in r8153b_queue_wake()
2808 ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); in r8153b_queue_wake()
2910 /* The bit 0 ~ 7 are relative with teredo settings. They are in r8153_teredo_off()
2913 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); in r8153_teredo_off()
2921 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); in r8153_teredo_off()
2922 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); in r8153_teredo_off()
2961 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_read()
2970 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_write()
3047 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); in r8152b_exit_oob()
3057 for (i = 0; i < 1000; i++) { in r8152b_exit_oob()
3068 for (i = 0; i < 1000; i++) { in r8152b_exit_oob()
3127 for (i = 0; i < 1000; i++) { in r8152b_enter_oob()
3138 for (i = 0; i < 1000; i++) { in r8152b_enter_oob()
3176 for (i = 0; request && i < 5000; i++) { in r8153_patch_request()
3187 return 0; in r8153_patch_request()
3204 for (i = 0; i < 20; i++) { in r8153_aldps_en()
3206 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) in r8153_aldps_en()
3217 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); in r8153b_aldps_en()
3219 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); in r8153b_aldps_en()
3247 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); in r8153b_eee_en()
3249 r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); in r8153b_eee_en()
3255 r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); in r8153b_enable_fc()
3268 ocp_reg_write(tp, OCP_EEE_ADV, 0); in r8153_hw_phy_cfg()
3286 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); in r8153_hw_phy_cfg()
3293 sram_write(tp, SRAM_LPF_CFG, 0xf70f); in r8153_hw_phy_cfg()
3296 sram_write(tp, SRAM_10M_AMP1, 0x00af); in r8153_hw_phy_cfg()
3297 sram_write(tp, SRAM_10M_AMP2, 0x0208); in r8153_hw_phy_cfg()
3333 u32 ocp_data, ups_flags = 0; in r8153b_hw_phy_cfg()
3341 ocp_reg_write(tp, OCP_EEE_ADV, 0); in r8153b_hw_phy_cfg()
3353 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake in r8153b_hw_phy_cfg()
3357 ocp_data = r8152_efuse_read(tp, 0x7d); in r8153b_hw_phy_cfg()
3358 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); in r8153b_hw_phy_cfg()
3359 if (data != 0xffff) in r8153b_hw_phy_cfg()
3363 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] in r8153b_hw_phy_cfg()
3366 ocp_data = ocp_reg_read(tp, 0xc426); in r8153b_hw_phy_cfg()
3367 ocp_data &= 0x3fff; in r8153b_hw_phy_cfg()
3391 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8153b_hw_phy_cfg()
3401 r8153b_ups_flags_w1w0(tp, ups_flags, 0); in r8153b_hw_phy_cfg()
3437 for (i = 0; i < 1000; i++) { in r8153_first_init()
3448 for (i = 0; i < 1000; i++) { in r8153_first_init()
3489 for (i = 0; i < 1000; i++) { in r8153_enter_oob()
3500 for (i = 0; i < 1000; i++) { in r8153_enter_oob()
3523 * type. Set it to zero. bits[7:0] are the W1C bits about in r8153_enter_oob()
3526 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in r8153_enter_oob()
3570 int ret = 0; in rtl8152_set_speed()
3579 gbcr = 0; in rtl8152_set_speed()
3584 bmcr = 0; in rtl8152_set_speed()
3666 for (i = 0; i < 50; i++) { in rtl8152_set_speed()
3668 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) in rtl8152_set_speed()
3776 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); in rtl8152_in_nway()
3777 tp->ocp_base = 0x2000; in rtl8152_in_nway()
3778 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ in rtl8152_in_nway()
3779 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); in rtl8152_in_nway()
3782 if (nway_state & 0xc000) in rtl8152_in_nway()
3790 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; in rtl8153_in_nway()
3843 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_work_func_t()
3850 schedule_delayed_work(&tp->schedule, 0); in rtl_work_func_t()
3878 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_hw_phy_work_func_t()
3922 int res = 0; in rtl8152_open()
3929 if (res < 0) in rtl8152_open()
3957 return 0; in rtl8152_open()
3971 int res = 0; in rtl8152_close()
3984 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { in rtl8152_close()
4065 for (i = 0; i < 500; i++) { in r8153_init()
4075 data = r8153_phy_status(tp, 0); in r8153_init()
4106 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
4113 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
4144 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); in r8153_init()
4186 for (i = 0; i < 500; i++) { in r8153b_init()
4196 data = r8153_phy_status(tp, 0); in r8153b_init()
4208 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153b_init()
4209 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153b_init()
4244 return 0; in rtl8152_pre_reset()
4248 return 0; in rtl8152_pre_reset()
4261 return 0; in rtl8152_pre_reset()
4270 return 0; in rtl8152_post_reset()
4274 return 0; in rtl8152_post_reset()
4292 return 0; in rtl8152_post_reset()
4354 return 0; in rtl8152_runtime_resume()
4370 return 0; in rtl8152_system_resume()
4376 int ret = 0; in rtl8152_runtime_suspend()
4382 u32 rcr = 0; in rtl8152_runtime_suspend()
4445 return 0; in rtl8152_system_suspend()
4488 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_reset_resume()
4497 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_wol()
4501 wol->supported = 0; in rtl8152_get_wol()
4502 wol->wolopts = 0; in rtl8152_get_wol()
4525 if (ret < 0) in rtl8152_set_wol()
4576 if (ret < 0) in rtl8152_get_link_ksettings()
4598 if (ret < 0) in rtl8152_set_link_ksettings()
4651 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_ethtool_stats()
4658 data[0] = le64_to_cpu(tally.tx_packets); in rtl8152_get_ethtool_stats()
4684 u32 ocp_data, lp, adv, supported = 0; in r8152_get_eee()
4705 return 0; in r8152_get_eee()
4715 val = 0; in r8152_set_eee()
4719 return 0; in r8152_set_eee()
4724 u32 ocp_data, lp, adv, supported = 0; in r8153_get_eee()
4745 return 0; in r8153_get_eee()
4755 val = 0; in r8153_set_eee()
4759 return 0; in r8153_set_eee()
4769 val = 0; in r8153b_set_eee()
4773 return 0; in r8153b_set_eee()
4783 if (ret < 0) in rtl_ethtool_get_eee()
4805 if (ret < 0) in rtl_ethtool_set_eee()
4828 if (ret < 0) in rtl8152_nway_reset()
4859 return 0; in rtl8152_get_coalesce()
4881 if (ret < 0) in rtl8152_set_coalesce()
4929 if (res < 0) in rtl8152_ioctl()
4973 return 0; in rtl8152_change_mtu()
4979 if (ret < 0) in rtl8152_change_mtu()
5044 int ret = 0; in rtl_ops_init()
5107 u32 ocp_data = 0; in rtl_get_version()
5114 return 0; in rtl_get_version()
5116 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in rtl_get_version()
5119 if (ret > 0) in rtl_get_version()
5125 case 0x4c00: in rtl_get_version()
5128 case 0x4c10: in rtl_get_version()
5131 case 0x5c00: in rtl_get_version()
5134 case 0x5c10: in rtl_get_version()
5137 case 0x5c20: in rtl_get_version()
5140 case 0x5c30: in rtl_get_version()
5143 case 0x4800: in rtl_get_version()
5146 case 0x6000: in rtl_get_version()
5149 case 0x6010: in rtl_get_version()
5154 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); in rtl_get_version()
5158 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); in rtl_get_version()
5192 tp->msg_enable = 0x7FFF; in rtl8152_probe()
5203 tp->mii.supports_gmii = 0; in rtl8152_probe()
5238 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && in rtl8152_probe()
5262 tp->mii.phy_id_mask = 0x3f; in rtl8152_probe()
5263 tp->mii.reg_num_mask = 0x1f; in rtl8152_probe()
5273 __rtl_set_wol(tp, 0); in rtl8152_probe()
5278 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_probe()
5285 if (ret != 0) { in rtl8152_probe()
5297 return 0; in rtl8152_probe()
5344 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5345 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5346 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5347 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5348 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5349 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
5350 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5351 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
5352 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
5353 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
5354 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
5355 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
5356 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
5357 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
5358 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5359 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
5360 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},