Lines Matching +full:auto +full:- +full:flow +full:- +full:control

3  * Copyright (C) 2007-2008 SMSC
50 /* SCSRs - System Control and Status Registers */
94 #define HW_CFG_ETC_		(0x00000010)	/* EEPROM Timeout Control */
108 /* Power Management Control Register */
136 /* Automatic Flow Control Configuration Register */
138 #define AFC_CFG_HI_		(0x00FF0000)	/* Auto Flow Ctrl High Level */
139 #define AFC_CFG_LO_		(0x0000FF00)	/* Auto Flow Ctrl Low Level */
141 #define AFC_CFG_FC_MULT_	(0x00000008)	/* Flow Ctrl on Mcast Frame */
142 #define AFC_CFG_FC_BRD_		(0x00000004)	/* Flow Ctrl on Bcast Frame */
143 #define AFC_CFG_FC_ADD_		(0x00000002)	/* Flow Ctrl on Addr. Decode */
144 #define AFC_CFG_FC_ANY_		(0x00000001)	/* Flow Ctrl on Any Frame */
179 #define	STRAP_STATUS_PWR_SEL_		(0x00000020) /* Device self-powered */
180 #define	STRAP_STATUS_AMDIX_EN_		(0x00000010) /* Auto-MDIX Enabled */
181 #define	STRAP_STATUS_PORT_SWAP_		(0x00000008) /* USBD+/USBD- Swapped */
204 /* Interrupt Endpoint Control Register */
221 /* MAC CSRs - MAC Control and Status Registers */
222 /* MAC Control Register */
234 #define MAC_CR_LCOLL_		(0x00001000)	/* Late Collision Control */
264 /* Flow Control Register */
265 #define FLOW			(0x11C)  macro
267 #define FLOW_FCPASS_		(0x00000004)	/* Pass Control Frames */
268 #define FLOW_FCEN_		(0x00000002)	/* Flow Control Enable */
269 #define FLOW_FCBSY_		(0x00000001)	/* Flow Control Busy */
282 /* Wake Up Control and Status Register */
291 /* Checksum Offload Engine Control Register */
297 /* Vendor-specific PHY Definitions (via MII access) */
315 /* Mode Control/Status Register */
320 /* Control/Status Indication Register */
341 /* PHY Special Control/Status Register */