4  * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved.
8  * Free Software Foundation; version 2 of the License and no later version.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
51 	VMXNET3_REG_RXPROD2	= 0xA00	 /* Rx Producer Index for ring 2 */
57 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
102  *	Little Endian layout of bitfields -
104  *	Byte 1 :	rsvd gen 13.len.8
105  *	Byte 2 : 	5.msscof.0 ext1  dtype
108  *	Big Endian layout of bitfields -
111  *	Byte 2 :	rsvd gen 13.len.8
127 	u32 gen:1;      /* generation bit */  member
131 	u32 gen:1;      /* generation bit */  member
144 	u32 om:2;       /* offload mode */
148 	u32 om:2;       /* offload mode */
159 #define VMXNET3_OM_CSUM		2
167 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
197 	u32		gen:1;        /* generation bit */  member
204 	u32		gen:1;        /* Generation bit */  member
214 	u32		gen:1;        /* Generation bit */  member
235 	u32		ext1:2;
239 	u32		ext1:2;
264 	u32		gen:1;        /* generation bit */  member
286 	u32		gen:1;        /* generation bit */  member
297 	u32		gen:1;        /* generation bit */  member
319 	u32		gen:1;        /* generation bit */  member
342 	VMXNET3_RCD_RSS_TYPE_TCPIPV4  = 2,
350 	__le64				qword[2];
366 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
369 /* max # of tx descs for a non-tso pkt */
373 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
380 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
384 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
388 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
392 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
427 	VMXNET3_GOS_BITS_64     = 2,
438 	u32		gosBits:2;    /* 32-bit or 64-bit? */
440 	u32		gosBits:2;     /* 32-bit or 64-bit? */
499 	__le64		rxRingBasePA[2];
503 	__le32		rxRingSize[2];   /* # of rx desc */
516 	VMXNET3_IMM_LAZY   = 2
522 	VMXNET3_IT_MSI  = 2,
542 	__le32		reserved[2];
650 	VMXNET3_COALESCE_STATIC     = 2,
694 	__le64					data[2];
698 	/* read-only region for device, read by dev in response to a SET cmd */
727 #define VMXNET3_ECR_LINK        (1 << 2)
731 /* flip the gen bit of a ring */
732 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)  argument
734 /* only use this if moving the idx won't affect the gen bit */