Lines Matching refs:d0
199 movel OR1, %d0
200 andl #0xF00007FF, %d0 // mask AMxx bits
201 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
202 movel %d0, OR1
206 clrl %d0 // D0 = 4 * port
207 init_1: tstl ch_status_addr(%d0)
209 addl #VALUE_WINDOW, ch_status_addr(%d0)
210 init_2: addl #4, %d0
211 cmpl #4 * 4, %d0
260 main_1: clrl %d0 // D0 = 4 * port
283 addl #4, %d0 // D0 = 4 * next port
284 cmpl #4 * 4, %d0
293 movel ch_status_addr(%d0), %a0 // A0 = port status address
298 clrl tx_in(%d0)
299 clrl tx_out(%d0)
300 clrl tx_count(%d0)
301 clrl rx_in(%d0)
304 andl clocking_mask(%d0), %d1
307 orl clocking_txfromrx(%d0), %d1
311 orl clocking_ext(%d0), %d1
315 orw #STATUS_CABLE_DTR, csr_output(%d0) // DTR on
319 movel first_buffer(%d0), %d1 // D1 = starting buffer address
320 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address
348 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address
349 movel scc_reg_addr(%d0), %a2 // A2 = SCC_REGS address
354 movel tx_first_bd(%d0), %d1
368 movew #2, parity_bytes(%d0)
378 movew #4, parity_bytes(%d0)
388 movew #2, parity_bytes(%d0)
398 movew #4, parity_bytes(%d0)
406 clrw parity_bytes(%d0)
419 movel %d0, %d1
435 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address
439 andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off
442 movel ch_status_addr(%d0), %d1
450 cmpl #TX_BUFFERS, tx_count(%d0)
453 movel tx_out(%d0), %d1
456 addl ch_status_addr(%d0), %d2
464 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr
473 movel tx_out(%d0), %d1
478 tx_1: movel %d1, tx_out(%d0)
480 addl #1, tx_count(%d0)
489 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#
491 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address
499 tstw parity_bytes(%d0)
508 subw parity_bytes(%d0), %d3 // D3 = packet length
526 movel packet_full(%d0), (%d2) // update desc stat
541 movel rx_in(%d0), %d1
546 rx_2: movel %d1, rx_in(%d0)
550 movel ch_status_addr(%d0), %d2
555 movel ch_status_addr(%d0), %d2
565 tx_end: tstl tx_count(%d0)
568 movel tx_in(%d0), %d1
571 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address
577 orl bell_tx(%d0), %d6 // signal host that TX desc freed
578 subl #1, tx_count(%d0)
579 movel tx_in(%d0), %d1
585 movel %d1, tx_in(%d0)
589 addl ch_status_addr(%d0), %d2
608 movel %d0, -(%sp)
611 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly
612 btstl #4, %d0 // transfer done?
619 movel %d0, -(%sp)
622 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly
623 btstl #12, %d0 // transfer done?
631 movel (%sp)+, %d0
643 movel %d0, -(%sp)
645 movel PLX_DOORBELL_TO_CARD, %d0
646 movel %d0, PLX_DOORBELL_TO_CARD // confirm all requests
647 orl %d0, channel_stats
651 movel (%sp)+, %d0
687 movel %d0, -(%sp)
693 clrl %d0 // D0 = 4 * port
728 movew csr_output(%d0), %d2
734 cmpw old_csr_output(%d0), %d1
736 movew %d1, old_csr_output(%d0)
741 andw dcd_mask(%d0), %d1
752 movel ch_status_addr(%d0), %a1
756 movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD // signal the host
760 addl #4, %d0 // D0 = 4 * next port
761 cmpl #4 * 4, %d0
768 movel (%sp)+, %d0
784 movel #128 * 1024, %d0 // D0 = RAM size tested
786 cmpl #MAX_RAM_SIZE, %d0
788 movel %d0, %a0
793 lsll #1, %d0
803 movel %d0, %a0 // A0 = fill ptr
804 subl #firmware_end + 4, %d0
805 lsrl #2, %d0
806 movel %d0, %d1 // D1 = DBf counter
816 dbnew %d0, ram_test_loop
818 subl #0x10000, %d0
819 cmpl #0xFFFFFFFF, %d0