Lines Matching +full:0 +full:x000000ff
31 #define RF2420 0x0000
32 #define RF2421 0x0001
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x014c
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0100
47 #define BBP_BASE 0x0000
48 #define BBP_SIZE 0x0020
49 #define RF_BASE 0x0004
50 #define RF_SIZE 0x000c
65 #define CSR0 0x0000
66 #define CSR0_REVISION FIELD32(0x0000ffff)
70 * SOFT_RESET: Software reset, 1: reset, 0: normal.
71 * BBP_RESET: Hardware reset, 1: reset, 0, release.
74 #define CSR1 0x0004
75 #define CSR1_SOFT_RESET FIELD32(0x00000001)
76 #define CSR1_BBP_RESET FIELD32(0x00000002)
77 #define CSR1_HOST_READY FIELD32(0x00000004)
82 #define CSR2 0x0008
85 * CSR3: STA MAC address register 0.
87 #define CSR3 0x000c
88 #define CSR3_BYTE0 FIELD32(0x000000ff)
89 #define CSR3_BYTE1 FIELD32(0x0000ff00)
90 #define CSR3_BYTE2 FIELD32(0x00ff0000)
91 #define CSR3_BYTE3 FIELD32(0xff000000)
96 #define CSR4 0x0010
97 #define CSR4_BYTE4 FIELD32(0x000000ff)
98 #define CSR4_BYTE5 FIELD32(0x0000ff00)
101 * CSR5: BSSID register 0.
103 #define CSR5 0x0014
104 #define CSR5_BYTE0 FIELD32(0x000000ff)
105 #define CSR5_BYTE1 FIELD32(0x0000ff00)
106 #define CSR5_BYTE2 FIELD32(0x00ff0000)
107 #define CSR5_BYTE3 FIELD32(0xff000000)
112 #define CSR6 0x0018
113 #define CSR6_BYTE4 FIELD32(0x000000ff)
114 #define CSR6_BYTE5 FIELD32(0x0000ff00)
127 #define CSR7 0x001c
128 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
129 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
130 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
131 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
132 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
133 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
134 #define CSR7_RXDONE FIELD32(0x00000040)
147 #define CSR8 0x0020
148 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
149 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
150 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
151 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
152 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
153 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
154 #define CSR8_RXDONE FIELD32(0x00000040)
160 #define CSR9 0x0024
161 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
171 #define CSR11 0x002c
172 #define CSR11_CWMIN FIELD32(0x0000000f)
173 #define CSR11_CWMAX FIELD32(0x000000f0)
174 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
175 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
176 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
179 * CSR12: Synchronization configuration register 0.
184 #define CSR12 0x0030
185 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
186 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
192 * CFP_PERIOD: Cfp period, default is 0 TU.
194 #define CSR13 0x0034
195 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
196 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
201 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
209 #define CSR14 0x0038
210 #define CSR14_TSF_COUNT FIELD32(0x00000001)
211 #define CSR14_TSF_SYNC FIELD32(0x00000006)
212 #define CSR14_TBCN FIELD32(0x00000008)
213 #define CSR14_TCFP FIELD32(0x00000010)
214 #define CSR14_TATIMW FIELD32(0x00000020)
215 #define CSR14_BEACON_GEN FIELD32(0x00000040)
216 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
217 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
225 #define CSR15 0x003c
226 #define CSR15_CFP FIELD32(0x00000001)
227 #define CSR15_ATIMW FIELD32(0x00000002)
228 #define CSR15_BEACON_SENT FIELD32(0x00000004)
231 * CSR16: TSF timer register 0.
233 #define CSR16 0x0040
234 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
239 #define CSR17 0x0044
240 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
243 * CSR18: IFS timer register 0.
247 #define CSR18 0x0048
248 #define CSR18_SIFS FIELD32(0x0000ffff)
249 #define CSR18_PIFS FIELD32(0xffff0000)
256 #define CSR19 0x004c
257 #define CSR19_DIFS FIELD32(0x0000ffff)
258 #define CSR19_EIFS FIELD32(0xffff0000)
266 #define CSR20 0x0050
267 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
268 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
269 #define CSR20_AUTOWAKE FIELD32(0x01000000)
274 * TYPE_93C46: 1: 93c46, 0:93c66.
276 #define CSR21 0x0054
277 #define CSR21_RELOAD FIELD32(0x00000001)
278 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
279 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
280 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
281 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
282 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
289 #define CSR22 0x0058
290 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
291 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
305 #define TXCSR0 0x0060
306 #define TXCSR0_KICK_TX FIELD32(0x00000001)
307 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
308 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
309 #define TXCSR0_ABORT FIELD32(0x00000008)
318 #define TXCSR1 0x0064
319 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
320 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
321 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
322 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
331 #define TXCSR2 0x0068
332 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
333 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
334 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
335 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
340 #define TXCSR3 0x006c
341 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
346 #define TXCSR4 0x0070
347 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
352 #define TXCSR5 0x0074
353 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
358 #define TXCSR6 0x0078
359 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
365 #define TXCSR7 0x007c
366 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
384 #define RXCSR0 0x0080
385 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
386 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
387 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
388 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
389 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
390 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
391 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
392 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
399 #define RXCSR1 0x0084
400 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
401 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
406 #define RXCSR2 0x0088
407 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
414 #define RXCSR3 0x0090
415 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
416 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
417 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
418 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
419 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
420 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
421 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
422 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
429 #define RXCSR4 0x0094
430 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
431 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
432 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
433 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
436 * ARCSR0: Auto Responder PLCP config register 0.
440 #define ARCSR0 0x0098
441 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
442 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
443 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
444 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
451 #define ARCSR1 0x009c
452 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
453 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
454 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
455 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
464 * BIG_ENDIAN: 1: big endian, 0: little endian.
466 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
468 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
469 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
472 #define PCICSR 0x008c
473 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
474 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
475 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
476 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
477 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
483 #define CNT0 0x00a0
484 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
494 #define TIMECSR2 0x00a8
495 #define CNT1 0x00ac
496 #define CNT2 0x00b0
497 #define TIMECSR3 0x00b4
498 #define CNT3 0x00b8
499 #define CNT4 0x00bc
500 #define CNT5 0x00c0
509 #define PWRCSR0 0x00c4
514 #define PSCSR0 0x00c8
515 #define PSCSR1 0x00cc
516 #define PSCSR2 0x00d0
517 #define PSCSR3 0x00d4
521 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
529 #define PWRCSR1 0x00d8
530 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
531 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
532 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
533 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
534 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
535 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
543 #define TIMECSR 0x00dc
544 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
545 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
546 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
549 * MACCSR0: MAC configuration register 0.
551 #define MACCSR0 0x00e0
560 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
563 #define MACCSR1 0x00e4
564 #define MACCSR1_KICK_RX FIELD32(0x00000001)
565 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
566 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
567 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
568 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
569 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
570 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
577 #define RALINKCSR 0x00e8
578 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
579 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
580 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
581 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
591 #define BCNCSR 0x00ec
592 #define BCNCSR_CHANGE FIELD32(0x00000001)
593 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
594 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
595 #define BCNCSR_MODE FIELD32(0x00006000)
596 #define BCNCSR_PLUS FIELD32(0x00008000)
607 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
609 #define BBPCSR 0x00f0
610 #define BBPCSR_VALUE FIELD32(0x000000ff)
611 #define BBPCSR_REGNUM FIELD32(0x00007f00)
612 #define BBPCSR_BUSY FIELD32(0x00008000)
613 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
619 * IF_SELECT: Chip to program: 0: rf, 1: if.
623 #define RFCSR 0x00f4
624 #define RFCSR_VALUE FIELD32(0x00ffffff)
625 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
626 #define RFCSR_IF_SELECT FIELD32(0x20000000)
627 #define RFCSR_PLL_LD FIELD32(0x40000000)
628 #define RFCSR_BUSY FIELD32(0x80000000)
634 * LINK: 0: linkoff, 1: linkup.
635 * ACTIVITY: 0: idle, 1: active.
637 #define LEDCSR 0x00f8
638 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
639 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
640 #define LEDCSR_LINK FIELD32(0x00010000)
641 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
650 #define RXPTR 0x0100
651 #define TXPTR 0x0104
652 #define PRIPTR 0x0108
653 #define ATIMPTR 0x010c
662 * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
664 #define GPIOCSR 0x0120
665 #define GPIOCSR_VAL0 FIELD32(0x00000001)
666 #define GPIOCSR_VAL1 FIELD32(0x00000002)
667 #define GPIOCSR_VAL2 FIELD32(0x00000004)
668 #define GPIOCSR_VAL3 FIELD32(0x00000008)
669 #define GPIOCSR_VAL4 FIELD32(0x00000010)
670 #define GPIOCSR_VAL5 FIELD32(0x00000020)
671 #define GPIOCSR_VAL6 FIELD32(0x00000040)
672 #define GPIOCSR_VAL7 FIELD32(0x00000080)
673 #define GPIOCSR_DIR0 FIELD32(0x00000100)
674 #define GPIOCSR_DIR1 FIELD32(0x00000200)
675 #define GPIOCSR_DIR2 FIELD32(0x00000400)
676 #define GPIOCSR_DIR3 FIELD32(0x00000800)
677 #define GPIOCSR_DIR4 FIELD32(0x00001000)
678 #define GPIOCSR_DIR5 FIELD32(0x00002000)
679 #define GPIOCSR_DIR6 FIELD32(0x00004000)
680 #define GPIOCSR_DIR7 FIELD32(0x00008000)
685 #define BBPPCSR 0x0124
691 #define BCNCSR1 0x0130
692 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
698 #define MACCSR2 0x0134
699 #define MACCSR2_DELAY FIELD32(0x000000ff)
704 #define ARCSR2 0x013c
705 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
706 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
707 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
708 #define ARCSR2_LENGTH FIELD32(0xffff0000)
713 #define ARCSR3 0x0140
714 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
715 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
716 #define ARCSR3_LENGTH FIELD32(0xffff0000)
721 #define ARCSR4 0x0144
722 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
723 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
724 #define ARCSR4_LENGTH FIELD32(0xffff0000)
729 #define ARCSR5 0x0148
730 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
731 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
732 #define ARCSR5_LENGTH FIELD32(0xffff0000)
742 #define BBP_R1_TX_ANTENNA FIELD8(0x03)
747 #define BBP_R4_RX_ANTENNA FIELD8(0x06)
756 #define RF1_TUNER FIELD32(0x00020000)
761 #define RF3_TUNER FIELD32(0x00000100)
762 #define RF3_TXPOWER FIELD32(0x00003e00)
772 #define EEPROM_MAC_ADDR_0 0x0002
773 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
774 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
775 #define EEPROM_MAC_ADDR1 0x0003
776 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
777 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
778 #define EEPROM_MAC_ADDR_2 0x0004
779 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
780 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
785 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
786 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
788 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
789 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
792 #define EEPROM_ANTENNA 0x0b
793 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
794 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
795 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
796 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
797 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
798 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
799 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
804 #define EEPROM_BBP_START 0x0c
806 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
807 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
812 #define EEPROM_TXPOWER_START 0x13
814 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
815 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
830 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
831 #define TXD_W0_VALID FIELD32(0x00000002)
832 #define TXD_W0_RESULT FIELD32(0x0000001c)
833 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
834 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
835 #define TXD_W0_ACK FIELD32(0x00000200)
836 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
837 #define TXD_W0_RTS FIELD32(0x00000800)
838 #define TXD_W0_IFS FIELD32(0x00006000)
839 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
840 #define TXD_W0_AGC FIELD32(0x00ff0000)
841 #define TXD_W0_R2 FIELD32(0xff000000)
846 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
851 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
852 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
858 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
859 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
860 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
861 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
862 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
863 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
865 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
866 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
867 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
868 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
869 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
870 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
875 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
876 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
877 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
878 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
879 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
884 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
889 #define TXD_W7_RESERVED FIELD32(0xffffffff)
898 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
899 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
900 #define RXD_W0_MULTICAST FIELD32(0x00000004)
901 #define RXD_W0_BROADCAST FIELD32(0x00000008)
902 #define RXD_W0_MY_BSS FIELD32(0x00000010)
903 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
904 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
905 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
910 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
915 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
916 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
917 #define RXD_W2_SIGNAL FIELD32(0xff000000)
922 #define RXD_W3_RSSI FIELD32(0x000000ff)
923 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
924 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
925 #define RXD_W3_BBR5 FIELD32(0xff000000)
930 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
935 #define RXD_W5_RESERVED FIELD32(0xffffffff)
936 #define RXD_W6_RESERVED FIELD32(0xffffffff)
937 #define RXD_W7_RESERVED FIELD32(0xffffffff)