Lines Matching full:pci
61 u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, in __dw_pcie_read_dbi() argument
67 if (pci->ops->read_dbi) in __dw_pcie_read_dbi()
68 return pci->ops->read_dbi(pci, base, reg, size); in __dw_pcie_read_dbi()
72 dev_err(pci->dev, "Read DBI address failed\n"); in __dw_pcie_read_dbi()
77 void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, in __dw_pcie_write_dbi() argument
82 if (pci->ops->write_dbi) { in __dw_pcie_write_dbi()
83 pci->ops->write_dbi(pci, base, reg, size, val); in __dw_pcie_write_dbi()
89 dev_err(pci->dev, "Write DBI address failed\n"); in __dw_pcie_write_dbi()
92 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ob_unroll() argument
96 return dw_pcie_readl_dbi(pci, offset + reg); in dw_pcie_readl_ob_unroll()
99 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ob_unroll() argument
104 dw_pcie_writel_dbi(pci, offset + reg, val); in dw_pcie_writel_ob_unroll()
107 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, in dw_pcie_prog_outbound_atu_unroll() argument
113 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, in dw_pcie_prog_outbound_atu_unroll()
115 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, in dw_pcie_prog_outbound_atu_unroll()
117 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, in dw_pcie_prog_outbound_atu_unroll()
119 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
121 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
123 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, in dw_pcie_prog_outbound_atu_unroll()
125 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_outbound_atu_unroll()
133 val = dw_pcie_readl_ob_unroll(pci, index, in dw_pcie_prog_outbound_atu_unroll()
140 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu_unroll()
143 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, in dw_pcie_prog_outbound_atu() argument
148 if (pci->ops->cpu_addr_fixup) in dw_pcie_prog_outbound_atu()
149 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in dw_pcie_prog_outbound_atu()
151 if (pci->iatu_unroll_enabled) { in dw_pcie_prog_outbound_atu()
152 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr, in dw_pcie_prog_outbound_atu()
157 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, in dw_pcie_prog_outbound_atu()
159 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, in dw_pcie_prog_outbound_atu()
161 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, in dw_pcie_prog_outbound_atu()
163 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, in dw_pcie_prog_outbound_atu()
165 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, in dw_pcie_prog_outbound_atu()
167 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, in dw_pcie_prog_outbound_atu()
169 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); in dw_pcie_prog_outbound_atu()
170 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); in dw_pcie_prog_outbound_atu()
177 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in dw_pcie_prog_outbound_atu()
183 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu()
186 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ib_unroll() argument
190 return dw_pcie_readl_dbi(pci, offset + reg); in dw_pcie_readl_ib_unroll()
193 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ib_unroll() argument
198 dw_pcie_writel_dbi(pci, offset + reg, val); in dw_pcie_writel_ib_unroll()
201 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, in dw_pcie_prog_inbound_atu_unroll() argument
208 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
210 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
224 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type); in dw_pcie_prog_inbound_atu_unroll()
225 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_inbound_atu_unroll()
234 val = dw_pcie_readl_ib_unroll(pci, index, in dw_pcie_prog_inbound_atu_unroll()
241 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu_unroll()
246 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, in dw_pcie_prog_inbound_atu() argument
252 if (pci->iatu_unroll_enabled) in dw_pcie_prog_inbound_atu()
253 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar, in dw_pcie_prog_inbound_atu()
256 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | in dw_pcie_prog_inbound_atu()
258 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
259 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
272 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); in dw_pcie_prog_inbound_atu()
273 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE in dw_pcie_prog_inbound_atu()
281 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in dw_pcie_prog_inbound_atu()
287 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
292 void dw_pcie_disable_atu(struct dw_pcie *pci, int index, in dw_pcie_disable_atu() argument
308 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); in dw_pcie_disable_atu()
309 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE); in dw_pcie_disable_atu()
312 int dw_pcie_wait_for_link(struct dw_pcie *pci) in dw_pcie_wait_for_link() argument
318 if (dw_pcie_link_up(pci)) { in dw_pcie_wait_for_link()
319 dev_info(pci->dev, "Link up\n"); in dw_pcie_wait_for_link()
325 dev_err(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
330 int dw_pcie_link_up(struct dw_pcie *pci) in dw_pcie_link_up() argument
334 if (pci->ops->link_up) in dw_pcie_link_up()
335 return pci->ops->link_up(pci); in dw_pcie_link_up()
337 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1); in dw_pcie_link_up()
342 void dw_pcie_setup(struct dw_pcie *pci) in dw_pcie_setup() argument
347 struct device *dev = pci->dev; in dw_pcie_setup()
355 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); in dw_pcie_setup()
371 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); in dw_pcie_setup()
374 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in dw_pcie_setup()
377 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_setup()
393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in dw_pcie_setup()