Lines Matching +full:pex +full:- +full:bias
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
219 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
334 writel(value, pcie->afi + offset); in afi_writel()
339 return readl(pcie->afi + offset); in afi_readl()
345 writel(value, pcie->pads + offset); in pads_writel()
350 return readl(pcie->pads + offset); in pads_readl()
385 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
388 if (bus->number == 0) { in tegra_pcie_map_bus()
392 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_map_bus()
393 if (port->index + 1 == slot) { in tegra_pcie_map_bus()
394 addr = port->base + (where & ~3); in tegra_pcie_map_bus()
402 offset = tegra_pcie_conf_offset(bus->number, devfn, where); in tegra_pcie_map_bus()
405 base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); in tegra_pcie_map_bus()
409 addr = pcie->cfg + (offset & (SZ_4K - 1)); in tegra_pcie_map_bus()
418 if (bus->number == 0) in tegra_pcie_config_read()
428 if (bus->number == 0) in tegra_pcie_config_write()
445 switch (port->index) { in tegra_pcie_port_get_pex_ctrl()
468 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
470 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
474 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
476 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
482 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_enable()
486 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_enable()
489 if (soc->has_pex_clkreq_en) in tegra_pcie_port_enable()
494 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_enable()
498 if (soc->force_pca_enable) { in tegra_pcie_port_enable()
499 value = readl(port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
501 writel(value, port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
508 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_disable()
512 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
514 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
517 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
519 if (soc->has_pex_clkreq_en) in tegra_pcie_port_disable()
523 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
528 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_port_free()
529 struct device *dev = pcie->dev; in tegra_pcie_port_free()
531 devm_iounmap(dev, port->base); in tegra_pcie_port_free()
532 devm_release_mem_region(dev, port->regs.start, in tegra_pcie_port_free()
533 resource_size(&port->regs)); in tegra_pcie_port_free()
534 list_del(&port->list); in tegra_pcie_port_free()
541 dev->class = PCI_CLASS_BRIDGE_PCI << 8; in tegra_pcie_fixup_class()
561 struct list_head *windows = &host->windows; in tegra_pcie_request_resources()
562 struct device *dev = pcie->dev; in tegra_pcie_request_resources()
565 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io); in tegra_pcie_request_resources()
566 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem); in tegra_pcie_request_resources()
567 pci_add_resource_offset(windows, &pcie->prefetch, pcie->offset.mem); in tegra_pcie_request_resources()
568 pci_add_resource(windows, &pcie->busn); in tegra_pcie_request_resources()
576 pci_remap_iospace(&pcie->pio, pcie->io.start); in tegra_pcie_request_resources()
584 struct list_head *windows = &host->windows; in tegra_pcie_free_resources()
586 pci_unmap_iospace(&pcie->pio); in tegra_pcie_free_resources()
592 struct tegra_pcie *pcie = pdev->bus->sysdata; in tegra_pcie_map_irq()
599 irq = pcie->irq; in tegra_pcie_map_irq()
624 struct device *dev = pcie->dev; in tegra_pcie_isr()
662 * - 0xfdfc000000: I/O space
663 * - 0xfdfe000000: type 0 configuration space
664 * - 0xfdff000000: type 1 configuration space
665 * - 0xfe00000000: type 0 extended configuration space
666 * - 0xfe10000000: type 1 extended configuration space
673 size = resource_size(&pcie->cs); in tegra_pcie_setup_translations()
674 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START); in tegra_pcie_setup_translations()
679 size = resource_size(&pcie->io); in tegra_pcie_setup_translations()
680 axi_address = pcie->io.start; in tegra_pcie_setup_translations()
686 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; in tegra_pcie_setup_translations()
687 size = resource_size(&pcie->prefetch); in tegra_pcie_setup_translations()
688 axi_address = pcie->prefetch.start; in tegra_pcie_setup_translations()
694 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; in tegra_pcie_setup_translations()
695 size = resource_size(&pcie->mem); in tegra_pcie_setup_translations()
696 axi_address = pcie->mem.start; in tegra_pcie_setup_translations()
725 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pll_wait()
731 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_pll_wait()
736 return -ETIMEDOUT; in tegra_pcie_pll_wait()
741 struct device *dev = pcie->dev; in tegra_pcie_phy_enable()
742 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_enable()
758 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
760 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; in tegra_pcie_phy_enable()
761 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
764 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
766 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
771 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
773 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
797 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_disable()
811 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
813 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
822 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_on()
826 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_on()
827 err = phy_power_on(port->phys[i]); in tegra_pcie_port_phy_power_on()
839 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_off()
843 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_off()
844 err = phy_power_off(port->phys[i]); in tegra_pcie_port_phy_power_off()
857 struct device *dev = pcie->dev; in tegra_pcie_phy_power_on()
858 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_power_on()
862 if (pcie->legacy_phy) { in tegra_pcie_phy_power_on()
863 if (pcie->phy) in tegra_pcie_phy_power_on()
864 err = phy_power_on(pcie->phy); in tegra_pcie_phy_power_on()
874 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_on()
879 port->index, err); in tegra_pcie_phy_power_on()
885 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); in tegra_pcie_phy_power_on()
887 if (soc->num_ports > 2) in tegra_pcie_phy_power_on()
888 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); in tegra_pcie_phy_power_on()
895 struct device *dev = pcie->dev; in tegra_pcie_phy_power_off()
899 if (pcie->legacy_phy) { in tegra_pcie_phy_power_off()
900 if (pcie->phy) in tegra_pcie_phy_power_off()
901 err = phy_power_off(pcie->phy); in tegra_pcie_phy_power_off()
911 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_off()
916 port->index, err); in tegra_pcie_phy_power_off()
926 struct device *dev = pcie->dev; in tegra_pcie_enable_controller()
927 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_controller()
933 if (pcie->phy) { in tegra_pcie_enable_controller()
940 /* power down PCIe slot clock bias pad */ in tegra_pcie_enable_controller()
941 if (soc->has_pex_bias_ctrl) in tegra_pcie_enable_controller()
947 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; in tegra_pcie_enable_controller()
949 list_for_each_entry(port, &pcie->ports, list) in tegra_pcie_enable_controller()
950 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_enable_controller()
954 if (soc->has_gen2) { in tegra_pcie_enable_controller()
964 if (soc->program_uphy) { in tegra_pcie_enable_controller()
973 reset_control_deassert(pcie->pcie_xrst); in tegra_pcie_enable_controller()
984 if (soc->has_intr_prsnt_sense) in tegra_pcie_enable_controller()
1003 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_disable_controller()
1005 if (pcie->soc->program_uphy) { in tegra_pcie_disable_controller()
1008 dev_err(pcie->dev, "failed to power off PHY(s): %d\n", in tegra_pcie_disable_controller()
1015 struct device *dev = pcie->dev; in tegra_pcie_power_off()
1016 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_off()
1019 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_off()
1020 reset_control_assert(pcie->pex_rst); in tegra_pcie_power_off()
1022 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1023 if (soc->has_cml_clk) in tegra_pcie_power_off()
1024 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_off()
1025 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_off()
1026 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_power_off()
1028 if (!dev->pm_domain) in tegra_pcie_power_off()
1031 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_off()
1038 struct device *dev = pcie->dev; in tegra_pcie_power_on()
1039 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_on()
1042 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_power_on()
1043 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_on()
1044 reset_control_assert(pcie->pex_rst); in tegra_pcie_power_on()
1046 if (!dev->pm_domain) in tegra_pcie_power_on()
1050 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1054 if (dev->pm_domain) { in tegra_pcie_power_on()
1055 err = clk_prepare_enable(pcie->pex_clk); in tegra_pcie_power_on()
1057 dev_err(dev, "failed to enable PEX clock: %d\n", err); in tegra_pcie_power_on()
1060 reset_control_deassert(pcie->pex_rst); in tegra_pcie_power_on()
1063 pcie->pex_clk, in tegra_pcie_power_on()
1064 pcie->pex_rst); in tegra_pcie_power_on()
1071 reset_control_deassert(pcie->afi_rst); in tegra_pcie_power_on()
1073 err = clk_prepare_enable(pcie->afi_clk); in tegra_pcie_power_on()
1079 if (soc->has_cml_clk) { in tegra_pcie_power_on()
1080 err = clk_prepare_enable(pcie->cml_clk); in tegra_pcie_power_on()
1087 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1098 struct device *dev = pcie->dev; in tegra_pcie_clocks_get()
1099 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_clocks_get()
1101 pcie->pex_clk = devm_clk_get(dev, "pex"); in tegra_pcie_clocks_get()
1102 if (IS_ERR(pcie->pex_clk)) in tegra_pcie_clocks_get()
1103 return PTR_ERR(pcie->pex_clk); in tegra_pcie_clocks_get()
1105 pcie->afi_clk = devm_clk_get(dev, "afi"); in tegra_pcie_clocks_get()
1106 if (IS_ERR(pcie->afi_clk)) in tegra_pcie_clocks_get()
1107 return PTR_ERR(pcie->afi_clk); in tegra_pcie_clocks_get()
1109 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1110 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1111 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
1113 if (soc->has_cml_clk) { in tegra_pcie_clocks_get()
1114 pcie->cml_clk = devm_clk_get(dev, "cml"); in tegra_pcie_clocks_get()
1115 if (IS_ERR(pcie->cml_clk)) in tegra_pcie_clocks_get()
1116 return PTR_ERR(pcie->cml_clk); in tegra_pcie_clocks_get()
1124 struct device *dev = pcie->dev; in tegra_pcie_resets_get()
1126 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex"); in tegra_pcie_resets_get()
1127 if (IS_ERR(pcie->pex_rst)) in tegra_pcie_resets_get()
1128 return PTR_ERR(pcie->pex_rst); in tegra_pcie_resets_get()
1130 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi"); in tegra_pcie_resets_get()
1131 if (IS_ERR(pcie->afi_rst)) in tegra_pcie_resets_get()
1132 return PTR_ERR(pcie->afi_rst); in tegra_pcie_resets_get()
1134 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x"); in tegra_pcie_resets_get()
1135 if (IS_ERR(pcie->pcie_xrst)) in tegra_pcie_resets_get()
1136 return PTR_ERR(pcie->pcie_xrst); in tegra_pcie_resets_get()
1143 struct device *dev = pcie->dev; in tegra_pcie_phys_get_legacy()
1146 pcie->phy = devm_phy_optional_get(dev, "pcie"); in tegra_pcie_phys_get_legacy()
1147 if (IS_ERR(pcie->phy)) { in tegra_pcie_phys_get_legacy()
1148 err = PTR_ERR(pcie->phy); in tegra_pcie_phys_get_legacy()
1153 err = phy_init(pcie->phy); in tegra_pcie_phys_get_legacy()
1159 pcie->legacy_phy = true; in tegra_pcie_phys_get_legacy()
1172 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index); in devm_of_phy_optional_get_index()
1174 return ERR_PTR(-ENOMEM); in devm_of_phy_optional_get_index()
1179 if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV) in devm_of_phy_optional_get_index()
1187 struct device *dev = port->pcie->dev; in tegra_pcie_port_get_phys()
1192 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); in tegra_pcie_port_get_phys()
1193 if (!port->phys) in tegra_pcie_port_get_phys()
1194 return -ENOMEM; in tegra_pcie_port_get_phys()
1196 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_get_phys()
1197 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i); in tegra_pcie_port_get_phys()
1211 port->phys[i] = phy; in tegra_pcie_port_get_phys()
1219 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phys_get()
1220 struct device_node *np = pcie->dev->of_node; in tegra_pcie_phys_get()
1224 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL) in tegra_pcie_phys_get()
1227 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_get()
1239 struct device *dev = pcie->dev; in tegra_pcie_phys_put()
1242 if (pcie->legacy_phy) { in tegra_pcie_phys_put()
1243 err = phy_exit(pcie->phy); in tegra_pcie_phys_put()
1249 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_put()
1250 for (i = 0; i < port->lanes; i++) { in tegra_pcie_phys_put()
1251 err = phy_exit(port->phys[i]); in tegra_pcie_phys_put()
1262 struct device *dev = pcie->dev; in tegra_pcie_get_resources()
1265 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_get_resources()
1280 if (soc->program_uphy) { in tegra_pcie_get_resources()
1289 pcie->pads = devm_ioremap_resource(dev, pads); in tegra_pcie_get_resources()
1290 if (IS_ERR(pcie->pads)) { in tegra_pcie_get_resources()
1291 err = PTR_ERR(pcie->pads); in tegra_pcie_get_resources()
1296 pcie->afi = devm_ioremap_resource(dev, afi); in tegra_pcie_get_resources()
1297 if (IS_ERR(pcie->afi)) { in tegra_pcie_get_resources()
1298 err = PTR_ERR(pcie->afi); in tegra_pcie_get_resources()
1305 err = -EADDRNOTAVAIL; in tegra_pcie_get_resources()
1309 pcie->cs = *res; in tegra_pcie_get_resources()
1312 pcie->cs.end = pcie->cs.start + SZ_4K - 1; in tegra_pcie_get_resources()
1314 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); in tegra_pcie_get_resources()
1315 if (IS_ERR(pcie->cfg)) { in tegra_pcie_get_resources()
1316 err = PTR_ERR(pcie->cfg); in tegra_pcie_get_resources()
1327 pcie->irq = err; in tegra_pcie_get_resources()
1329 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); in tegra_pcie_get_resources()
1338 if (soc->program_uphy) in tegra_pcie_get_resources()
1345 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_put_resources()
1347 if (pcie->irq > 0) in tegra_pcie_put_resources()
1348 free_irq(pcie->irq, pcie); in tegra_pcie_put_resources()
1350 if (soc->program_uphy) in tegra_pcie_put_resources()
1358 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_pme_turnoff()
1359 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pme_turnoff()
1365 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1368 ack_bit = soc->ports[port->index].pme.ack_bit; in tegra_pcie_pme_turnoff()
1369 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, in tegra_pcie_pme_turnoff()
1372 dev_err(pcie->dev, "PME Ack is not received on port: %d\n", in tegra_pcie_pme_turnoff()
1373 port->index); in tegra_pcie_pme_turnoff()
1378 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1386 mutex_lock(&chip->lock); in tegra_msi_alloc()
1388 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR); in tegra_msi_alloc()
1390 set_bit(msi, chip->used); in tegra_msi_alloc()
1392 msi = -ENOSPC; in tegra_msi_alloc()
1394 mutex_unlock(&chip->lock); in tegra_msi_alloc()
1401 struct device *dev = chip->chip.dev; in tegra_msi_free()
1403 mutex_lock(&chip->lock); in tegra_msi_free()
1405 if (!test_bit(irq, chip->used)) in tegra_msi_free()
1408 clear_bit(irq, chip->used); in tegra_msi_free()
1410 mutex_unlock(&chip->lock); in tegra_msi_free()
1416 struct device *dev = pcie->dev; in tegra_pcie_msi_irq()
1417 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_irq()
1431 irq = irq_find_mapping(msi->domain, index); in tegra_pcie_msi_irq()
1433 if (test_bit(index, msi->used)) in tegra_pcie_msi_irq()
1467 irq = irq_create_mapping(msi->domain, hwirq); in tegra_msi_setup_irq()
1470 return -EINVAL; in tegra_msi_setup_irq()
1475 msg.address_lo = lower_32_bits(msi->phys); in tegra_msi_setup_irq()
1476 msg.address_hi = upper_32_bits(msi->phys); in tegra_msi_setup_irq()
1507 irq_set_chip_data(irq, domain->host_data); in tegra_msi_map()
1521 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_msi_setup()
1522 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_setup()
1523 struct device *dev = pcie->dev; in tegra_pcie_msi_setup()
1526 mutex_init(&msi->lock); in tegra_pcie_msi_setup()
1528 msi->chip.dev = dev; in tegra_pcie_msi_setup()
1529 msi->chip.setup_irq = tegra_msi_setup_irq; in tegra_pcie_msi_setup()
1530 msi->chip.teardown_irq = tegra_msi_teardown_irq; in tegra_pcie_msi_setup()
1532 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR, in tegra_pcie_msi_setup()
1533 &msi_domain_ops, &msi->chip); in tegra_pcie_msi_setup()
1534 if (!msi->domain) { in tegra_pcie_msi_setup()
1536 return -ENOMEM; in tegra_pcie_msi_setup()
1545 msi->irq = err; in tegra_pcie_msi_setup()
1547 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD, in tegra_pcie_msi_setup()
1555 msi->pages = __get_free_pages(GFP_KERNEL, 0); in tegra_pcie_msi_setup()
1556 msi->phys = virt_to_phys((void *)msi->pages); in tegra_pcie_msi_setup()
1557 host->msi = &msi->chip; in tegra_pcie_msi_setup()
1562 irq_domain_remove(msi->domain); in tegra_pcie_msi_setup()
1568 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_msi()
1569 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_enable_msi()
1572 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); in tegra_pcie_enable_msi()
1573 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); in tegra_pcie_enable_msi()
1595 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_teardown()
1598 free_pages(msi->pages, 0); in tegra_pcie_msi_teardown()
1600 if (msi->irq > 0) in tegra_pcie_msi_teardown()
1601 free_irq(msi->irq, pcie); in tegra_pcie_msi_teardown()
1604 irq = irq_find_mapping(msi->domain, i); in tegra_pcie_msi_teardown()
1609 irq_domain_remove(msi->domain); in tegra_pcie_msi_teardown()
1637 struct device *dev = pcie->dev; in tegra_pcie_get_xbar_config()
1638 struct device_node *np = dev->of_node; in tegra_pcie_get_xbar_config()
1640 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_xbar_config()
1664 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") || in tegra_pcie_get_xbar_config()
1665 of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_xbar_config()
1677 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_xbar_config()
1694 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_xbar_config()
1697 dev_info(dev, "single-mode configuration\n"); in tegra_pcie_get_xbar_config()
1702 dev_info(dev, "dual-mode configuration\n"); in tegra_pcie_get_xbar_config()
1708 return -EINVAL; in tegra_pcie_get_xbar_config()
1724 snprintf(property, 32, "%s-supply", supplies[i].supply); in of_regulator_bulk_available()
1736 * number of cases but is not future proof. However to preserve backwards-
1742 struct device *dev = pcie->dev; in tegra_pcie_get_legacy_regulators()
1743 struct device_node *np = dev->of_node; in tegra_pcie_get_legacy_regulators()
1745 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) in tegra_pcie_get_legacy_regulators()
1746 pcie->num_supplies = 3; in tegra_pcie_get_legacy_regulators()
1747 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) in tegra_pcie_get_legacy_regulators()
1748 pcie->num_supplies = 2; in tegra_pcie_get_legacy_regulators()
1750 if (pcie->num_supplies == 0) { in tegra_pcie_get_legacy_regulators()
1752 return -ENODEV; in tegra_pcie_get_legacy_regulators()
1755 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_legacy_regulators()
1756 sizeof(*pcie->supplies), in tegra_pcie_get_legacy_regulators()
1758 if (!pcie->supplies) in tegra_pcie_get_legacy_regulators()
1759 return -ENOMEM; in tegra_pcie_get_legacy_regulators()
1761 pcie->supplies[0].supply = "pex-clk"; in tegra_pcie_get_legacy_regulators()
1762 pcie->supplies[1].supply = "vdd"; in tegra_pcie_get_legacy_regulators()
1764 if (pcie->num_supplies > 2) in tegra_pcie_get_legacy_regulators()
1765 pcie->supplies[2].supply = "avdd"; in tegra_pcie_get_legacy_regulators()
1767 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies); in tegra_pcie_get_legacy_regulators()
1781 struct device *dev = pcie->dev; in tegra_pcie_get_regulators()
1782 struct device_node *np = dev->of_node; in tegra_pcie_get_regulators()
1785 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_regulators()
1786 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
1788 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1789 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1791 if (!pcie->supplies) in tegra_pcie_get_regulators()
1792 return -ENOMEM; in tegra_pcie_get_regulators()
1794 pcie->supplies[i++].supply = "dvdd-pex"; in tegra_pcie_get_regulators()
1795 pcie->supplies[i++].supply = "hvdd-pex-pll"; in tegra_pcie_get_regulators()
1796 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1797 pcie->supplies[i++].supply = "vddio-pexctl-aud"; in tegra_pcie_get_regulators()
1798 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_regulators()
1799 pcie->num_supplies = 6; in tegra_pcie_get_regulators()
1801 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1802 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1804 if (!pcie->supplies) in tegra_pcie_get_regulators()
1805 return -ENOMEM; in tegra_pcie_get_regulators()
1807 pcie->supplies[i++].supply = "avdd-pll-uerefe"; in tegra_pcie_get_regulators()
1808 pcie->supplies[i++].supply = "hvddio-pex"; in tegra_pcie_get_regulators()
1809 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
1810 pcie->supplies[i++].supply = "dvdd-pex-pll"; in tegra_pcie_get_regulators()
1811 pcie->supplies[i++].supply = "hvdd-pex-pll-e"; in tegra_pcie_get_regulators()
1812 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
1813 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { in tegra_pcie_get_regulators()
1814 pcie->num_supplies = 7; in tegra_pcie_get_regulators()
1816 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1817 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1819 if (!pcie->supplies) in tegra_pcie_get_regulators()
1820 return -ENOMEM; in tegra_pcie_get_regulators()
1822 pcie->supplies[i++].supply = "avddio-pex"; in tegra_pcie_get_regulators()
1823 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
1824 pcie->supplies[i++].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
1825 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1826 pcie->supplies[i++].supply = "hvdd-pex-pll-e"; in tegra_pcie_get_regulators()
1827 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
1828 pcie->supplies[i++].supply = "avdd-pll-erefe"; in tegra_pcie_get_regulators()
1829 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_regulators()
1840 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + in tegra_pcie_get_regulators()
1843 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1844 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1846 if (!pcie->supplies) in tegra_pcie_get_regulators()
1847 return -ENOMEM; in tegra_pcie_get_regulators()
1849 pcie->supplies[i++].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
1850 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1851 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
1852 pcie->supplies[i++].supply = "avdd-plle"; in tegra_pcie_get_regulators()
1855 pcie->supplies[i++].supply = "avdd-pexa"; in tegra_pcie_get_regulators()
1856 pcie->supplies[i++].supply = "vdd-pexa"; in tegra_pcie_get_regulators()
1860 pcie->supplies[i++].supply = "avdd-pexb"; in tegra_pcie_get_regulators()
1861 pcie->supplies[i++].supply = "vdd-pexb"; in tegra_pcie_get_regulators()
1863 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_regulators()
1864 pcie->num_supplies = 5; in tegra_pcie_get_regulators()
1866 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1867 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1869 if (!pcie->supplies) in tegra_pcie_get_regulators()
1870 return -ENOMEM; in tegra_pcie_get_regulators()
1872 pcie->supplies[0].supply = "avdd-pex"; in tegra_pcie_get_regulators()
1873 pcie->supplies[1].supply = "vdd-pex"; in tegra_pcie_get_regulators()
1874 pcie->supplies[2].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
1875 pcie->supplies[3].supply = "avdd-plle"; in tegra_pcie_get_regulators()
1876 pcie->supplies[4].supply = "vddio-pex-clk"; in tegra_pcie_get_regulators()
1879 if (of_regulator_bulk_available(dev->of_node, pcie->supplies, in tegra_pcie_get_regulators()
1880 pcie->num_supplies)) in tegra_pcie_get_regulators()
1881 return devm_regulator_bulk_get(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1882 pcie->supplies); in tegra_pcie_get_regulators()
1891 devm_kfree(dev, pcie->supplies); in tegra_pcie_get_regulators()
1892 pcie->num_supplies = 0; in tegra_pcie_get_regulators()
1899 struct device *dev = pcie->dev; in tegra_pcie_parse_dt()
1900 struct device_node *np = dev->of_node, *port; in tegra_pcie_parse_dt()
1901 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_parse_dt()
1911 return -EINVAL; in tegra_pcie_parse_dt()
1921 /* Track the bus -> CPU I/O mapping offset. */ in tegra_pcie_parse_dt()
1922 pcie->offset.io = res.start - range.pci_addr; in tegra_pcie_parse_dt()
1924 memcpy(&pcie->pio, &res, sizeof(res)); in tegra_pcie_parse_dt()
1925 pcie->pio.name = np->full_name; in tegra_pcie_parse_dt()
1935 pcie->io.start = range.cpu_addr; in tegra_pcie_parse_dt()
1936 pcie->io.end = range.cpu_addr + range.size - 1; in tegra_pcie_parse_dt()
1937 pcie->io.flags = IORESOURCE_MEM; in tegra_pcie_parse_dt()
1938 pcie->io.name = "I/O"; in tegra_pcie_parse_dt()
1940 memcpy(&res, &pcie->io, sizeof(res)); in tegra_pcie_parse_dt()
1945 * Track the bus -> CPU memory mapping offset. This in tegra_pcie_parse_dt()
1946 * assumes that the prefetchable and non-prefetchable in tegra_pcie_parse_dt()
1950 pcie->offset.mem = res.start - range.pci_addr; in tegra_pcie_parse_dt()
1953 memcpy(&pcie->prefetch, &res, sizeof(res)); in tegra_pcie_parse_dt()
1954 pcie->prefetch.name = "prefetchable"; in tegra_pcie_parse_dt()
1956 memcpy(&pcie->mem, &res, sizeof(res)); in tegra_pcie_parse_dt()
1957 pcie->mem.name = "non-prefetchable"; in tegra_pcie_parse_dt()
1963 err = of_pci_parse_bus_range(np, &pcie->busn); in tegra_pcie_parse_dt()
1966 pcie->busn.name = np->name; in tegra_pcie_parse_dt()
1967 pcie->busn.start = 0; in tegra_pcie_parse_dt()
1968 pcie->busn.end = 0xff; in tegra_pcie_parse_dt()
1969 pcie->busn.flags = IORESOURCE_BUS; in tegra_pcie_parse_dt()
1986 if (index < 1 || index > soc->num_ports) { in tegra_pcie_parse_dt()
1988 err = -EINVAL; in tegra_pcie_parse_dt()
1992 index--; in tegra_pcie_parse_dt()
1994 err = of_property_read_u32(port, "nvidia,num-lanes", &value); in tegra_pcie_parse_dt()
2003 err = -EINVAL; in tegra_pcie_parse_dt()
2014 mask |= ((1 << value) - 1) << lane; in tegra_pcie_parse_dt()
2019 err = -ENOMEM; in tegra_pcie_parse_dt()
2023 err = of_address_to_resource(port, 0, &rp->regs); in tegra_pcie_parse_dt()
2029 INIT_LIST_HEAD(&rp->list); in tegra_pcie_parse_dt()
2030 rp->index = index; in tegra_pcie_parse_dt()
2031 rp->lanes = value; in tegra_pcie_parse_dt()
2032 rp->pcie = pcie; in tegra_pcie_parse_dt()
2033 rp->np = port; in tegra_pcie_parse_dt()
2035 rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs); in tegra_pcie_parse_dt()
2036 if (IS_ERR(rp->base)) in tegra_pcie_parse_dt()
2037 return PTR_ERR(rp->base); in tegra_pcie_parse_dt()
2039 list_add_tail(&rp->list, &pcie->ports); in tegra_pcie_parse_dt()
2042 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
2067 struct device *dev = port->pcie->dev; in tegra_pcie_port_check_link()
2072 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2075 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2081 value = readl(port->base + RP_VEND_XP); in tegra_pcie_port_check_link()
2087 } while (--timeout); in tegra_pcie_port_check_link()
2090 dev_err(dev, "link %u down, retrying\n", port->index); in tegra_pcie_port_check_link()
2097 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_port_check_link()
2103 } while (--timeout); in tegra_pcie_port_check_link()
2107 } while (--retries); in tegra_pcie_port_check_link()
2114 struct device *dev = pcie->dev; in tegra_pcie_enable_ports()
2117 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2119 port->index, port->lanes); in tegra_pcie_enable_ports()
2126 dev_info(dev, "link %u down, ignoring\n", port->index); in tegra_pcie_enable_ports()
2137 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_disable_ports()
2241 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2242 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2243 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2244 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2245 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2251 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_start()
2253 if (list_empty(&pcie->ports)) in tegra_pcie_ports_seq_start()
2258 return seq_list_start(&pcie->ports, *pos); in tegra_pcie_ports_seq_start()
2263 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_next()
2265 return seq_list_next(v, &pcie->ports, pos); in tegra_pcie_ports_seq_next()
2280 value = readl(port->base + RP_VEND_XP); in tegra_pcie_ports_seq_show()
2285 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_ports_seq_show()
2290 seq_printf(s, "%2u ", port->index); in tegra_pcie_ports_seq_show()
2315 struct tegra_pcie *pcie = inode->i_private; in tegra_pcie_ports_open()
2323 s = file->private_data; in tegra_pcie_ports_open()
2324 s->private = pcie; in tegra_pcie_ports_open()
2339 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_debugfs_exit()
2340 pcie->debugfs = NULL; in tegra_pcie_debugfs_exit()
2347 pcie->debugfs = debugfs_create_dir("pcie", NULL); in tegra_pcie_debugfs_init()
2348 if (!pcie->debugfs) in tegra_pcie_debugfs_init()
2349 return -ENOMEM; in tegra_pcie_debugfs_init()
2351 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, in tegra_pcie_debugfs_init()
2360 return -ENOMEM; in tegra_pcie_debugfs_init()
2365 struct device *dev = &pdev->dev; in tegra_pcie_probe()
2373 return -ENOMEM; in tegra_pcie_probe()
2376 host->sysdata = pcie; in tegra_pcie_probe()
2379 pcie->soc = of_device_get_match_data(dev); in tegra_pcie_probe()
2380 INIT_LIST_HEAD(&pcie->ports); in tegra_pcie_probe()
2381 pcie->dev = dev; in tegra_pcie_probe()
2399 pm_runtime_enable(pcie->dev); in tegra_pcie_probe()
2400 err = pm_runtime_get_sync(pcie->dev); in tegra_pcie_probe()
2410 host->busnr = pcie->busn.start; in tegra_pcie_probe()
2411 host->dev.parent = &pdev->dev; in tegra_pcie_probe()
2412 host->ops = &tegra_pcie_ops; in tegra_pcie_probe()
2413 host->map_irq = tegra_pcie_map_irq; in tegra_pcie_probe()
2414 host->swizzle_irq = pci_common_swizzle; in tegra_pcie_probe()
2422 pci_bus_size_bridges(host->bus); in tegra_pcie_probe()
2423 pci_bus_assign_resources(host->bus); in tegra_pcie_probe()
2425 list_for_each_entry(child, &host->bus->children, node) in tegra_pcie_probe()
2428 pci_bus_add_devices(host->bus); in tegra_pcie_probe()
2441 pm_runtime_put_sync(pcie->dev); in tegra_pcie_probe()
2442 pm_runtime_disable(pcie->dev); in tegra_pcie_probe()
2458 pci_stop_root_bus(host->bus); in tegra_pcie_remove()
2459 pci_remove_root_bus(host->bus); in tegra_pcie_remove()
2461 pm_runtime_put_sync(pcie->dev); in tegra_pcie_remove()
2462 pm_runtime_disable(pcie->dev); in tegra_pcie_remove()
2469 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_remove()
2480 list_for_each_entry(port, &pcie->ports, list) in tegra_pcie_pm_suspend()
2532 .name = "tegra-pcie",