18 #define PEM_CFG_WR 0x28
19 #define PEM_CFG_RD 0x30
33 	if (devfn != 0 || where >= 2048) {  in thunder_pem_bridge_read()
34 		*val = ~0;  in thunder_pem_bridge_read()
53 	case 0x40:  in thunder_pem_bridge_read()
54 		read_val &= 0xffff00ff;  in thunder_pem_bridge_read()
55 		read_val |= 0x00007000; /* Skip MSI CAP */  in thunder_pem_bridge_read()
57 	case 0x70: /* Express Cap */  in thunder_pem_bridge_read()
60 		 * reads as 0, else leave it alone.  in thunder_pem_bridge_read()
62 		if (!(read_val & (0x1f << 25)))  in thunder_pem_bridge_read()
65 	case 0xb0: /* MSI-X Cap */  in thunder_pem_bridge_read()
67 		read_val &= 0xc00000ff;  in thunder_pem_bridge_read()
69 		 * If Express Cap(0x70) raw PME vector reads as 0 we are on  in thunder_pem_bridge_read()
73 		writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);  in thunder_pem_bridge_read()
76 		if (!(tmp_val & (0x1f << 25)))  in thunder_pem_bridge_read()
77 			read_val |= 0x0003bc00;  in thunder_pem_bridge_read()
79 			read_val |= 0x0001bc00;  in thunder_pem_bridge_read()
81 	case 0xb4:  in thunder_pem_bridge_read()
82 		/* Table offset=0, BIR=0 */  in thunder_pem_bridge_read()
83 		read_val = 0x00000000;  in thunder_pem_bridge_read()
85 	case 0xb8:  in thunder_pem_bridge_read()
86 		/* BPA offset=0xf0000, BIR=0 */  in thunder_pem_bridge_read()
87 		read_val = 0x000f0000;  in thunder_pem_bridge_read()
89 	case 0xbc:  in thunder_pem_bridge_read()
91 		read_val = 0x00010014;  in thunder_pem_bridge_read()
93 	case 0xc0:  in thunder_pem_bridge_read()
95 		read_val = 0x00000000;  in thunder_pem_bridge_read()
97 	case 0xc4:  in thunder_pem_bridge_read()
98 		/* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */  in thunder_pem_bridge_read()
99 		read_val = 0x80ff0003;  in thunder_pem_bridge_read()
101 	case 0xc8:  in thunder_pem_bridge_read()
102 		read_val = pem_pci->ea_entry[0];  in thunder_pem_bridge_read()
104 	case 0xcc:  in thunder_pem_bridge_read()
107 	case 0xd0:  in thunder_pem_bridge_read()
116 		read_val &= 0xff;  in thunder_pem_bridge_read()
119 		read_val &= 0xffff;  in thunder_pem_bridge_read()
154 	u32 w1c_bits = 0;  in thunder_pem_bridge_w1c_bits()
157 	case 0x04: /* Command/Status */  in thunder_pem_bridge_w1c_bits()
158 	case 0x1c: /* Base and I/O Limit/Secondary Status */  in thunder_pem_bridge_w1c_bits()
159 		w1c_bits = 0xff000000;  in thunder_pem_bridge_w1c_bits()
161 	case 0x44: /* Power Management Control and Status */  in thunder_pem_bridge_w1c_bits()
162 		w1c_bits = 0xfffffe00;  in thunder_pem_bridge_w1c_bits()
164 	case 0x78: /* Device Control/Device Status */  in thunder_pem_bridge_w1c_bits()
165 	case 0x80: /* Link Control/Link Status */  in thunder_pem_bridge_w1c_bits()
166 	case 0x88: /* Slot Control/Slot Status */  in thunder_pem_bridge_w1c_bits()
167 	case 0x90: /* Root Status */  in thunder_pem_bridge_w1c_bits()
168 	case 0xa0: /* Link Control 2 Registers/Link Status 2 */  in thunder_pem_bridge_w1c_bits()
169 		w1c_bits = 0xffff0000;  in thunder_pem_bridge_w1c_bits()
171 	case 0x104: /* Uncorrectable Error Status */  in thunder_pem_bridge_w1c_bits()
172 	case 0x110: /* Correctable Error Status */  in thunder_pem_bridge_w1c_bits()
173 	case 0x130: /* Error Status */  in thunder_pem_bridge_w1c_bits()
174 	case 0x160: /* Link Control 4 */  in thunder_pem_bridge_w1c_bits()
175 		w1c_bits = 0xffffffff;  in thunder_pem_bridge_w1c_bits()
189 	case 0x1c: /* I/O Base / I/O Limit, Secondary Status */  in thunder_pem_bridge_w1_bits()
191 		w1_bits = 0x0101;  in thunder_pem_bridge_w1_bits()
193 	case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */  in thunder_pem_bridge_w1_bits()
195 		w1_bits = 0x00010001;  in thunder_pem_bridge_w1_bits()
198 		w1_bits = 0;  in thunder_pem_bridge_w1_bits()
211 	u32 mask = 0;  in thunder_pem_bridge_write()
214 	if (devfn != 0 || where >= 2048)  in thunder_pem_bridge_write()
228 		mask = ~(0xff << (8 * (where & 3)));  in thunder_pem_bridge_write()
230 		val = (val & 0xff) << (8 * (where & 3));  in thunder_pem_bridge_write()
237 		mask = ~(0xffff << (8 * (where & 3)));  in thunder_pem_bridge_write()
239 		val = (val & 0xffff) << (8 * (where & 3));  in thunder_pem_bridge_write()
306 	pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);  in thunder_pem_init()
316 	bar4_start = res_pem->start + 0xf00000;  in thunder_pem_init()
317 	pem_pci->ea_entry[0] = (u32)bar4_start | 2;  in thunder_pem_init()
322 	return 0;  in thunder_pem_init()
327 #define PEM_RES_BASE		0x87e0c0000000UL
361 		node = 0;  in thunder_pem_legacy_fw()