Lines Matching +full:non +full:- +full:prefetchable
1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
136 /* PCI BASE bits (PCI -> Local Bus) */
143 /* PCI MAP bits (PCI -> Local bus) */
152 /* LB_BASE0,1 bits (Local bus -> PCI) */
174 /* LB_MAP0,1 bits (Local bus -> PCI) */
187 /* LB_BASE2 bits (Local bus -> PCI IO) */
194 /* LB_MAP2 bits (Local bus -> PCI IO) */
231 /* ARM Integrator-specific extended control registers */
262 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
263 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
264 * 60000000 - 60FFFFFF PCI IO. 16M
265 * 61000000 - 61FFFFFF PCI Configuration. 16M
277 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
278 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
279 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
280 * Cfg 61000000 - 61FFFFFF
288 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
289 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
290 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
291 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
318 struct v3_pci *v3 = bus->sysdata; in v3_map_bus()
321 busnr = bus->number; in v3_map_bus()
328 * build the PCI configuration "address" with one-hot in in v3_map_bus()
329 * A31-A11 in v3_map_bus()
342 mapaddress |= BIT(slot - 5); in v3_map_bus()
367 * prefetchable), this frees up base1 for re-use by in v3_map_bus()
370 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
372 v3->base + V3_LB_BASE0); in v3_map_bus()
378 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
380 v3->base + V3_LB_BASE1); in v3_map_bus()
381 writew(mapaddress, v3->base + V3_LB_MAP1); in v3_map_bus()
383 return v3->config_base + address + offset; in v3_map_bus()
389 * Reassign base1 for use by prefetchable PCI memory in v3_unmap_bus()
391 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_unmap_bus()
394 v3->base + V3_LB_BASE1); in v3_unmap_bus()
395 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_unmap_bus()
397 v3->base + V3_LB_MAP1); in v3_unmap_bus()
402 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_unmap_bus()
404 v3->base + V3_LB_BASE0); in v3_unmap_bus()
410 struct v3_pci *v3 = bus->sysdata; in v3_pci_read_config()
413 dev_dbg(&bus->dev, in v3_pci_read_config()
424 struct v3_pci *v3 = bus->sysdata; in v3_pci_write_config()
427 dev_dbg(&bus->dev, in v3_pci_write_config()
444 struct device *dev = v3->dev; in v3_irq()
447 status = readw(v3->base + V3_PCI_STAT); in v3_irq()
456 writew(status, v3->base + V3_PCI_STAT); in v3_irq()
458 status = readb(v3->base + V3_LB_ISTAT); in v3_irq()
462 dev_err(dev, "PCI target LB->PCI READ abort interrupt\n"); in v3_irq()
464 dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n"); in v3_irq()
476 writeb(0, v3->base + V3_LB_ISTAT); in v3_irq()
477 if (v3->map) in v3_irq()
478 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_irq()
489 v3->map = in v3_integrator_init()
490 syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon"); in v3_integrator_init()
491 if (IS_ERR(v3->map)) { in v3_integrator_init()
492 dev_err(v3->dev, "no syscon\n"); in v3_integrator_init()
493 return -ENODEV; in v3_integrator_init()
496 regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val); in v3_integrator_init()
498 regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET, in v3_integrator_init()
507 writel(0x6200, v3->base + V3_LB_IO_BASE); in v3_integrator_init()
511 writeb(0xaa, v3->base + V3_MAIL_DATA); in v3_integrator_init()
512 writeb(0x55, v3->base + V3_MAIL_DATA + 4); in v3_integrator_init()
513 } while (readb(v3->base + V3_MAIL_DATA) != 0xaa && in v3_integrator_init()
514 readb(v3->base + V3_MAIL_DATA) != 0x55); in v3_integrator_init()
517 dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n"); in v3_integrator_init()
527 struct device *dev = v3->dev; in v3_pci_setup_resource()
532 switch (resource_type(win->res)) { in v3_pci_setup_resource()
534 io = win->res; in v3_pci_setup_resource()
535 io->name = "V3 PCI I/O"; in v3_pci_setup_resource()
536 v3->io_mem = io_base; in v3_pci_setup_resource()
537 v3->io_bus_addr = io->start - win->offset; in v3_pci_setup_resource()
539 io, &v3->io_bus_addr); in v3_pci_setup_resource()
547 /* Setup window 2 - PCI I/O */ in v3_pci_setup_resource()
548 writel(v3_addr_to_lb_base2(v3->io_mem) | in v3_pci_setup_resource()
550 v3->base + V3_LB_BASE2); in v3_pci_setup_resource()
551 writew(v3_addr_to_lb_map2(v3->io_bus_addr), in v3_pci_setup_resource()
552 v3->base + V3_LB_MAP2); in v3_pci_setup_resource()
555 mem = win->res; in v3_pci_setup_resource()
556 if (mem->flags & IORESOURCE_PREFETCH) { in v3_pci_setup_resource()
557 mem->name = "V3 PCI PRE-MEM"; in v3_pci_setup_resource()
558 v3->pre_mem = mem->start; in v3_pci_setup_resource()
559 v3->pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
560 dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n", in v3_pci_setup_resource()
561 mem, &v3->pre_bus_addr); in v3_pci_setup_resource()
563 dev_err(dev, "prefetchable memory range is not 256MB\n"); in v3_pci_setup_resource()
564 return -EINVAL; in v3_pci_setup_resource()
566 if (v3->non_pre_mem && in v3_pci_setup_resource()
567 (mem->start != v3->non_pre_mem + SZ_256M)) { in v3_pci_setup_resource()
569 "prefetchable memory is not adjacent to non-prefetchable memory\n"); in v3_pci_setup_resource()
570 return -EINVAL; in v3_pci_setup_resource()
572 /* Setup window 1 - PCI prefetchable memory */ in v3_pci_setup_resource()
573 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_pci_setup_resource()
577 v3->base + V3_LB_BASE1); in v3_pci_setup_resource()
578 writew(v3_addr_to_lb_map(v3->pre_bus_addr) | in v3_pci_setup_resource()
580 v3->base + V3_LB_MAP1); in v3_pci_setup_resource()
582 mem->name = "V3 PCI NON-PRE-MEM"; in v3_pci_setup_resource()
583 v3->non_pre_mem = mem->start; in v3_pci_setup_resource()
584 v3->non_pre_bus_addr = mem->start - win->offset; in v3_pci_setup_resource()
585 dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n", in v3_pci_setup_resource()
586 mem, &v3->non_pre_bus_addr); in v3_pci_setup_resource()
589 "non-prefetchable memory range is not 256MB\n"); in v3_pci_setup_resource()
590 return -EINVAL; in v3_pci_setup_resource()
592 /* Setup window 0 - PCI non-prefetchable memory */ in v3_pci_setup_resource()
593 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_pci_setup_resource()
596 v3->base + V3_LB_BASE0); in v3_pci_setup_resource()
597 writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) | in v3_pci_setup_resource()
599 v3->base + V3_LB_MAP0); in v3_pci_setup_resource()
603 dev_dbg(dev, "BUS %pR\n", win->res); in v3_pci_setup_resource()
604 host->busnr = win->res->start; in v3_pci_setup_resource()
608 resource_type(win->res)); in v3_pci_setup_resource()
619 struct device *dev = v3->dev; in v3_get_dma_range_config()
620 u64 cpu_end = range->cpu_addr + range->size - 1; in v3_get_dma_range_config()
621 u64 pci_end = range->pci_addr + range->size - 1; in v3_get_dma_range_config()
624 if (range->pci_addr & ~V3_PCI_BASE_M_ADR_BASE) { in v3_get_dma_range_config()
626 return -EINVAL; in v3_get_dma_range_config()
628 val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE; in v3_get_dma_range_config()
631 if (range->cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) { in v3_get_dma_range_config()
633 return -EINVAL; in v3_get_dma_range_config()
635 val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR; in v3_get_dma_range_config()
637 switch (range->size) { in v3_get_dma_range_config()
675 dev_err(v3->dev, "illegal dma memory chunk size\n"); in v3_get_dma_range_config()
676 return -EINVAL; in v3_get_dma_range_config()
683 "DMA MEM CPU: 0x%016llx -> 0x%016llx => " in v3_get_dma_range_config()
684 "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n", in v3_get_dma_range_config()
685 range->cpu_addr, cpu_end, in v3_get_dma_range_config()
686 range->pci_addr, pci_end, in v3_get_dma_range_config()
697 struct device *dev = v3->dev; in v3_pci_parse_map_dma_ranges()
701 dev_err(dev, "missing dma-ranges property\n"); in v3_pci_parse_map_dma_ranges()
702 return -EINVAL; in v3_pci_parse_map_dma_ranges()
706 * Get the dma-ranges from the device tree in v3_pci_parse_map_dma_ranges()
717 writel(pci_base, v3->base + V3_PCI_BASE0); in v3_pci_parse_map_dma_ranges()
718 writel(pci_map, v3->base + V3_PCI_MAP0); in v3_pci_parse_map_dma_ranges()
720 writel(pci_base, v3->base + V3_PCI_BASE1); in v3_pci_parse_map_dma_ranges()
721 writel(pci_map, v3->base + V3_PCI_MAP1); in v3_pci_parse_map_dma_ranges()
733 struct device *dev = &pdev->dev; in v3_pci_probe()
734 struct device_node *np = dev->of_node; in v3_pci_probe()
748 return -ENOMEM; in v3_pci_probe()
750 host->dev.parent = dev; in v3_pci_probe()
751 host->ops = &v3_pci_ops; in v3_pci_probe()
752 host->busnr = 0; in v3_pci_probe()
753 host->msi = NULL; in v3_pci_probe()
754 host->map_irq = of_irq_parse_and_map_pci; in v3_pci_probe()
755 host->swizzle_irq = pci_common_swizzle; in v3_pci_probe()
757 host->sysdata = v3; in v3_pci_probe()
758 v3->dev = dev; in v3_pci_probe()
773 v3->base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
774 if (IS_ERR(v3->base)) in v3_pci_probe()
775 return PTR_ERR(v3->base); in v3_pci_probe()
781 if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16)) in v3_pci_probe()
783 readl(v3->base + V3_LB_IO_BASE), regs); in v3_pci_probe()
789 return -EINVAL; in v3_pci_probe()
791 v3->config_mem = regs->start; in v3_pci_probe()
792 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
793 if (IS_ERR(v3->config_base)) in v3_pci_probe()
794 return PTR_ERR(v3->config_base); in v3_pci_probe()
809 return -ENODEV; in v3_pci_probe()
823 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) in v3_pci_probe()
824 writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM); in v3_pci_probe()
827 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
829 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
832 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
834 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
837 val = readw(v3->base + V3_PCI_CFG); in v3_pci_probe()
839 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
842 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
847 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
850 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
852 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
871 writel(0x00000000, v3->base + V3_PCI_IO_BASE); in v3_pci_probe()
879 writew(val, v3->base + V3_PCI_CFG); in v3_pci_probe()
890 v3->base + V3_FIFO_PRIORITY); in v3_pci_probe()
897 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
898 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
900 writew(val, v3->base + V3_LB_CFG); in v3_pci_probe()
902 v3->base + V3_LB_IMASK); in v3_pci_probe()
905 if (of_device_is_compatible(np, "arm,integrator-ap-pci")) { in v3_pci_probe()
911 /* Post-init: enable PCI memory and invalidate (master already on) */ in v3_pci_probe()
912 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
914 writew(val, v3->base + V3_PCI_CMD); in v3_pci_probe()
917 writeb(0, v3->base + V3_LB_ISTAT); in v3_pci_probe()
920 v3->base + V3_LB_IMASK); in v3_pci_probe()
923 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
925 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
928 * Re-lock the system register. in v3_pci_probe()
930 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
932 writew(val, v3->base + V3_SYSTEM); in v3_pci_probe()
934 list_splice_init(&res, &host->windows); in v3_pci_probe()
940 v3->bus = host->bus; in v3_pci_probe()
942 pci_bus_assign_resources(v3->bus); in v3_pci_probe()
943 pci_bus_add_devices(v3->bus); in v3_pci_probe()
950 .compatible = "v3,v360epc-pci",
957 .name = "pci-v3-semi",