1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
12 #include "pcie-cadence.h"
15  * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
23  * @max_regions: maximum number of regions supported by the hardware
24  * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
46 	struct cdns_pcie *pcie = &rc->pcie;  in cdns_pci_map_bus()
47 	unsigned int busn = bus->number;  in cdns_pci_map_bus()
50 	if (busn == rc->bus_range->start) {  in cdns_pci_map_bus()
59 		return pcie->reg_base + (where & 0xfff);  in cdns_pci_map_bus()
64 	/* Clear AXI link-down status */  in cdns_pci_map_bus()
80 	if (busn == rc->bus_range->start + 1)  in cdns_pci_map_bus()
86 	return rc->cfg_base + (where & 0xfff);  in cdns_pci_map_bus()
96 	{ .compatible = "cdns,cdns-pcie-host" },
103 	struct cdns_pcie *pcie = &rc->pcie;  in cdns_pcie_host_init_root_port()
109 	 * - disable both BAR0 and BAR1.  in cdns_pcie_host_init_root_port()
110 	 * - enable Prefetchable Memory Base and Limit registers in type 1  in cdns_pcie_host_init_root_port()
112 	 * - enable IO Base and Limit registers in type 1 config  in cdns_pcie_host_init_root_port()
125 	if (rc->vendor_id != 0xffff) {  in cdns_pcie_host_init_root_port()
126 		id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) |  in cdns_pcie_host_init_root_port()
127 			CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id);  in cdns_pcie_host_init_root_port()
131 	if (rc->device_id != 0xffff)  in cdns_pcie_host_init_root_port()
132 		cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);  in cdns_pcie_host_init_root_port()
143 	struct cdns_pcie *pcie = &rc->pcie;  in cdns_pcie_host_init_address_translation()
144 	struct resource *cfg_res = rc->cfg_res;  in cdns_pcie_host_init_address_translation()
145 	struct resource *mem_res = pcie->mem_res;  in cdns_pcie_host_init_address_translation()
146 	struct resource *bus_range = rc->bus_range;  in cdns_pcie_host_init_address_translation()
147 	struct device *dev = rc->dev;  in cdns_pcie_host_init_address_translation()
148 	struct device_node *np = dev->of_node;  in cdns_pcie_host_init_address_translation()
161 	desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);  in cdns_pcie_host_init_address_translation()
165 	cpu_addr = cfg_res->start - mem_res->start;  in cdns_pcie_host_init_address_translation()
180 		if (r >= rc->max_regions)  in cdns_pcie_host_init_address_translation()
203 	addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits);  in cdns_pcie_host_init_address_translation()
223 	rc->bus_range = bus_range;  in cdns_pcie_host_init()
224 	rc->pcie.bus = bus_range->start;  in cdns_pcie_host_init()
244 	struct device *dev = &pdev->dev;  in cdns_pcie_host_probe()
245 	struct device_node *np = dev->of_node;  in cdns_pcie_host_probe()
256 		return -ENOMEM;  in cdns_pcie_host_probe()
259 	rc->dev = dev;  in cdns_pcie_host_probe()
261 	pcie = &rc->pcie;  in cdns_pcie_host_probe()
262 	pcie->is_rc = true;  in cdns_pcie_host_probe()
264 	rc->max_regions = 32;  in cdns_pcie_host_probe()
265 	of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);  in cdns_pcie_host_probe()
267 	rc->no_bar_nbits = 32;  in cdns_pcie_host_probe()
268 	of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);  in cdns_pcie_host_probe()
270 	rc->vendor_id = 0xffff;  in cdns_pcie_host_probe()
271 	of_property_read_u16(np, "vendor-id", &rc->vendor_id);  in cdns_pcie_host_probe()
273 	rc->device_id = 0xffff;  in cdns_pcie_host_probe()
274 	of_property_read_u16(np, "device-id", &rc->device_id);  in cdns_pcie_host_probe()
279 		return -EINVAL;  in cdns_pcie_host_probe()
283 	pcie->reg_base = devm_ioremap_resource(dev, res);  in cdns_pcie_host_probe()
284 	if (IS_ERR(pcie->reg_base)) {  in cdns_pcie_host_probe()
286 		return PTR_ERR(pcie->reg_base);  in cdns_pcie_host_probe()
290 	rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);  in cdns_pcie_host_probe()
291 	if (IS_ERR(rc->cfg_base)) {  in cdns_pcie_host_probe()
293 		return PTR_ERR(rc->cfg_base);  in cdns_pcie_host_probe()
295 	rc->cfg_res = res;  in cdns_pcie_host_probe()
300 		return -EINVAL;  in cdns_pcie_host_probe()
302 	pcie->mem_res = res;  in cdns_pcie_host_probe()
322 	list_splice_init(&resources, &bridge->windows);  in cdns_pcie_host_probe()
323 	bridge->dev.parent = dev;  in cdns_pcie_host_probe()
324 	bridge->busnr = pcie->bus;  in cdns_pcie_host_probe()
325 	bridge->ops = &cdns_pcie_host_ops;  in cdns_pcie_host_probe()
326 	bridge->map_irq = of_irq_parse_and_map_pci;  in cdns_pcie_host_probe()
327 	bridge->swizzle_irq = pci_common_swizzle;  in cdns_pcie_host_probe()
344 	phy_count = pcie->phy_count;  in cdns_pcie_host_probe()
345 	while (phy_count--)  in cdns_pcie_host_probe()
346 		device_link_del(pcie->link[phy_count]);  in cdns_pcie_host_probe()
353 	struct device *dev = &pdev->dev;  in cdns_pcie_shutdown()
367 		.name = "cdns-pcie-host",