Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
66 /* derive the enum index of the outbound/inbound mapping registers */
70 * Maximum number of outbound mapping window sizes that can be supported by any
95 * iProc PCIe outbound mapping controller specific parameters
97 * @window_sizes: list of supported outbound mapping window sizes in MB
98 * @nr_sizes: number of supported outbound mapping window sizes
165 * @imap_addr_offset: register offset between the upper and lower 32-bit
270 /* outbound address mapping */
393 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
405 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
416 return readl(pcie->base + offset); in iproc_pcie_read_reg()
427 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
433 * (typically seen during enumeration with multi-function devices) from
442 if (bus->number && pcie->has_apb_err_disable) { in iproc_pcie_apb_err_disable()
474 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
494 * Note that a non-Vendor ID config register may have a value of in iproc_pcie_cfg_retry()
500 while (data == CFG_RETRY_STATUS && timeout--) { in iproc_pcie_cfg_retry()
525 pcie->fix_paxc_cap = true; in iproc_pcie_fix_cap()
529 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
537 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
560 unsigned int busno = bus->number; in iproc_pcie_config_read()
583 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pcie_config_read()
598 if (pcie->rej_unconfig_pf && in iproc_pcie_config_read()
630 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
640 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, in iproc_pcie_bus_map_cfg_bus()
659 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pci_raw_config_read32()
680 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
695 if (pcie->iproc_cfg_read) in iproc_pcie_config_read32()
731 if (pcie->ep_is_internal) in iproc_pcie_perst_ctrl()
759 struct device *dev = pcie->dev; in iproc_pcie_check_link()
767 if (pcie->ep_is_internal) in iproc_pcie_check_link()
773 return -ENODEV; in iproc_pcie_check_link()
780 return -EFAULT; in iproc_pcie_check_link()
827 return link_is_active ? 0 : -ENODEV; in iproc_pcie_check_link()
848 struct device *dev = pcie->dev; in iproc_pcie_ob_write()
861 return -EINVAL; in iproc_pcie_ob_write()
864 * Program the OARR registers. The upper 32-bit OARR register is in iproc_pcie_ob_write()
865 * always right after the lower 32-bit OARR register. in iproc_pcie_ob_write()
868 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
869 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
872 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
873 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
878 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
879 readl(pcie->base + oarr_offset + 4)); in iproc_pcie_ob_write()
881 readl(pcie->base + omap_offset), in iproc_pcie_ob_write()
882 readl(pcie->base + omap_offset + 4)); in iproc_pcie_ob_write()
888 * Some iProc SoCs require the SW to configure the outbound address mapping
890 * Outbound address translation:
892 * iproc_pcie_address = axi_address - axi_offset
896 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
901 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_setup_ob()
902 struct device *dev = pcie->dev; in iproc_pcie_setup_ob()
903 int ret = -EINVAL, window_idx, size_idx; in iproc_pcie_setup_ob()
905 if (axi_addr < ob->axi_offset) { in iproc_pcie_setup_ob()
907 &axi_addr, &ob->axi_offset); in iproc_pcie_setup_ob()
908 return -EINVAL; in iproc_pcie_setup_ob()
915 axi_addr -= ob->axi_offset; in iproc_pcie_setup_ob()
918 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { in iproc_pcie_setup_ob()
920 &pcie->ob_map[window_idx]; in iproc_pcie_setup_ob()
923 * If current outbound window is already in use, move on to the in iproc_pcie_setup_ob()
934 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; in iproc_pcie_setup_ob()
935 size_idx--) { in iproc_pcie_setup_ob()
937 ob_map->window_sizes[size_idx] * SZ_1M; in iproc_pcie_setup_ob()
947 return -EINVAL; in iproc_pcie_setup_ob()
959 size -= window_size; in iproc_pcie_setup_ob()
975 dev_err(dev, "unable to configure outbound mapping\n"); in iproc_pcie_setup_ob()
978 &axi_addr, &ob->axi_offset, &pci_addr, &size); in iproc_pcie_setup_ob()
986 struct device *dev = pcie->dev; in iproc_pcie_map_ranges()
991 struct resource *res = window->res; in iproc_pcie_map_ranges()
999 ret = iproc_pcie_setup_ob(pcie, res->start, in iproc_pcie_map_ranges()
1000 res->start - window->offset, in iproc_pcie_map_ranges()
1007 return -EINVAL; in iproc_pcie_map_ranges()
1017 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_is_in_use()
1022 return !!(val & (BIT(ib_map->nr_sizes) - 1)); in iproc_pcie_ib_is_in_use()
1028 return !!(ib_map->type == type); in iproc_pcie_ib_check_type()
1035 struct device *dev = pcie->dev; in iproc_pcie_ib_write()
1036 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_write()
1047 return -EINVAL; in iproc_pcie_ib_write()
1053 * Program the IARR registers. The upper 32-bit IARR register is in iproc_pcie_ib_write()
1054 * always right after the lower 32-bit IARR register. in iproc_pcie_ib_write()
1057 pcie->base + iarr_offset); in iproc_pcie_ib_write()
1058 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); in iproc_pcie_ib_write()
1061 readl(pcie->base + iarr_offset), in iproc_pcie_ib_write()
1062 readl(pcie->base + iarr_offset + 4)); in iproc_pcie_ib_write()
1070 val = readl(pcie->base + imap_offset); in iproc_pcie_ib_write()
1072 writel(val, pcie->base + imap_offset); in iproc_pcie_ib_write()
1074 pcie->base + imap_offset + ib_map->imap_addr_offset); in iproc_pcie_ib_write()
1077 window_idx, readl(pcie->base + imap_offset), in iproc_pcie_ib_write()
1078 readl(pcie->base + imap_offset + in iproc_pcie_ib_write()
1079 ib_map->imap_addr_offset)); in iproc_pcie_ib_write()
1081 imap_offset += ib_map->imap_window_offset; in iproc_pcie_ib_write()
1092 struct device *dev = pcie->dev; in iproc_pcie_setup_ib()
1093 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_setup_ib()
1096 u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr; in iproc_pcie_setup_ib()
1097 resource_size_t size = range->size; in iproc_pcie_setup_ib()
1099 /* iterate through all IARR mapping regions */ in iproc_pcie_setup_ib()
1100 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { in iproc_pcie_setup_ib()
1102 &pcie->ib_map[region_idx]; in iproc_pcie_setup_ib()
1113 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { in iproc_pcie_setup_ib()
1115 ib_map->region_sizes[size_idx] * ib_map->size_unit; in iproc_pcie_setup_ib()
1125 return -EINVAL; in iproc_pcie_setup_ib()
1130 ib_map->nr_windows, axi_addr, in iproc_pcie_setup_ib()
1139 ret = -EINVAL; in iproc_pcie_setup_ib()
1155 /* Get the dma-ranges from DT */ in iproc_pcie_map_dma_ranges()
1156 ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node); in iproc_pcie_map_dma_ranges()
1174 struct device *dev = pcie->dev; in iproce_pcie_get_msi()
1179 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1182 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { in iproce_pcie_get_msi()
1184 return -ENODEV; in iproce_pcie_get_msi()
1205 range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1); in iproc_pcie_paxb_v2_msi_steer()
1219 * treated as non-MSI transfers in iproc_pcie_paxc_v2_msi_steer()
1230 * based SoCs, all I/O register bases are well below the 32-bit in iproc_pcie_paxc_v2_msi_steer()
1263 struct device *dev = pcie->dev; in iproc_pcie_msi_steer()
1273 switch (pcie->type) { in iproc_pcie_msi_steer()
1283 return -EINVAL; in iproc_pcie_msi_steer()
1295 * Either the "msi-parent" or the "msi-map" phandle needs to exist in iproc_pcie_msi_enable()
1299 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); in iproc_pcie_msi_enable()
1305 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); in iproc_pcie_msi_enable()
1307 return -ENODEV; in iproc_pcie_msi_enable()
1312 return -ENODEV; in iproc_pcie_msi_enable()
1320 if (pcie->need_msi_steer) { in iproc_pcie_msi_enable()
1340 struct device *dev = pcie->dev; in iproc_pcie_rev_init()
1344 switch (pcie->type) { in iproc_pcie_rev_init()
1350 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1351 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1352 pcie->ob_map = paxb_ob_map; in iproc_pcie_rev_init()
1353 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); in iproc_pcie_rev_init()
1358 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1359 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1360 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1361 pcie->ob_map = paxb_v2_ob_map; in iproc_pcie_rev_init()
1362 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); in iproc_pcie_rev_init()
1364 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); in iproc_pcie_rev_init()
1365 pcie->ib_map = paxb_v2_ib_map; in iproc_pcie_rev_init()
1366 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1372 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1373 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1374 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1378 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1379 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1380 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1381 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1385 return -EINVAL; in iproc_pcie_rev_init()
1388 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1389 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1391 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1392 return -ENOMEM; in iproc_pcie_rev_init()
1395 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1398 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
1411 dev = pcie->dev; in iproc_pcie_setup()
1423 ret = phy_init(pcie->phy); in iproc_pcie_setup()
1429 ret = phy_power_on(pcie->phy); in iproc_pcie_setup()
1438 if (pcie->need_ob_cfg) { in iproc_pcie_setup()
1446 if (pcie->need_ib_cfg) { in iproc_pcie_setup()
1448 if (ret && ret != -ENOENT) in iproc_pcie_setup()
1464 list_splice_init(res, &host->windows); in iproc_pcie_setup()
1465 host->busnr = 0; in iproc_pcie_setup()
1466 host->dev.parent = dev; in iproc_pcie_setup()
1467 host->ops = &iproc_pcie_ops; in iproc_pcie_setup()
1468 host->sysdata = pcie; in iproc_pcie_setup()
1469 host->map_irq = pcie->map_irq; in iproc_pcie_setup()
1470 host->swizzle_irq = pci_common_swizzle; in iproc_pcie_setup()
1478 pci_assign_unassigned_bus_resources(host->bus); in iproc_pcie_setup()
1480 pcie->root_bus = host->bus; in iproc_pcie_setup()
1482 list_for_each_entry(child, &host->bus->children, node) in iproc_pcie_setup()
1485 pci_bus_add_devices(host->bus); in iproc_pcie_setup()
1490 phy_power_off(pcie->phy); in iproc_pcie_setup()
1492 phy_exit(pcie->phy); in iproc_pcie_setup()
1499 pci_stop_root_bus(pcie->root_bus); in iproc_pcie_remove()
1500 pci_remove_root_bus(pcie->root_bus); in iproc_pcie_remove()
1504 phy_power_off(pcie->phy); in iproc_pcie_remove()
1505 phy_exit(pcie->phy); in iproc_pcie_remove()
1517 struct iproc_pcie *pcie = iproc_data(pdev->bus); in quirk_paxc_disable_msi_parsing()
1519 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_disable_msi_parsing()
1536 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_bridge()
1537 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; in quirk_paxc_bridge()
1543 * so that the MPS can be set to the real max value. in quirk_paxc_bridge()
1545 pdev->pcie_mpss = 2; in quirk_paxc_bridge()